Adaptive 128-bit floating point load and store instructions for

Details Adaptive 128-bit floating point load and store instructions for Adaptive 128-bit floating point load and store instructions for

1995-12-20

1998-06-09

Coleman, Eric

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711212, G06F 500

Patent

active

057649596

ABSTRACT:
A technique for providing adaptive 128-bit load and store operations to support architecture extensions for computations on a 128-bit quadruple precision format, in which a single set of load and store instructions provides for save and restore operations on both 80-bit and 128-bit floating point register files. A 128-bit load and store instructions are utilized for moving values that are 128-bit aligned in memory. The transfer entails the movement of data between a 128-bit memory boundary and a floating point register file for register save and restore operations. In one embodiment, 80-bit registers are used and in a second embodiment 128-bit registers are used. The same instructions operate on both the 80-bit and 128-bit registers to map the content of a given register into a 128-bit boundary field in memory. A load/store unit allocates the bit positioning so that when 80-bit registers are used, the 80 bits are moved into the most significant bit positions of the 128-bit boundary field. The remaining bit positions are filled with 0s. When values are moved to memory the reverse operation is performed.

REFERENCES:
patent: 5410682 (1995-04-01), Sites
patent: 5559969 (1996-09-01), Jennings
patent: 5615385 (1997-03-01), Fetterman
IEEE Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Std 754-1985).
IEEE Standard for Radix-Independent Floating-Point Arithmetic (ANSI/IEEE Std 854-1987).
MC88110 Second Generation RISC Microprocessor User's Manual; Motorola Inc., 1991.

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