Adapter for the connection to a clear-channel telecommunication

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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Details

375294, 375375, 3701001, 3701053, H03D 324, H04J 306

Patent

active

055197370

ABSTRACT:
An adapter having a line interface circuit for providing an analog attachment to a network (100). The line interface circuit is provided with a reset input for beginning a resynchronization of the timing of the adapter. The adapter further includes a Digital Phase-locked Loop device DPLL (203) driven by a master clock (306) which provides the timing and synchronization signals to the line interface circuits (201). The DPLL (203) divides a master clock down to an internal INT clock (309), a phase comparator (303) compares the INT clock with a reference signal (302) which is synchronized with the receive clock (202) extracted from the line by line interface (201). The phase comparison process operates with a Correction Signal (CS) which has a window centered around the falling edge of the INT clock. A frequency correction is initiated when the reference clock falls outside of the correction window and is achieved by inserting or suppressing a master clock pulse at this time. The adapter further includes means for resetting the line interface circuits and the DPLL at the power-on of the adapter, such that the frequency correction apparatus of the adapter causes two adapters attached at separate ends of a transmission medium to evolve toward stable timing states with respect to each other.

REFERENCES:
patent: 4140975 (1979-02-01), Cochran et al.
patent: 4860285 (1989-08-01), Miller et al.
patent: 5125009 (1992-06-01), DeVilbiss
patent: 5311511 (1994-05-01), Reilly et al.
TBD, vol. 29, No. 2, Jul. 1986, "Clock Recovery Circuit Based on Preset Counter".
Data Communications, RS499: cornerstone for the 1980s, by Hardeman, pp. 67-71.
A VLSI Device Provides 144 KBPS Full Duplex Data Transmission Supporting ISDN Basic, by Mannone, Ontario pp. 670-673, Paper No. 85296 Session 29.

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