Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2004-07-02
2009-11-24
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
07624315
ABSTRACT:
One embodiment of the invention provides an adapter card for connection to a data bus in a data processing unit. The adapter includes a DDR interface for connection of a DDR memory module, a memory unit for storing test mode data, a switching device, which, in a first switching state, connects the data bus to the DDR interface and, in a second switching state, decouples the DDR interface from the data bus and connects the memory unit to the DDR interface such that test mode data may be transmitted to a connected DDR memory module to call up a test mode in the DDR memory module. The adapter also includes a control circuit with a trigger input to control the switching device between the switching states depending on a trigger signal.
REFERENCES:
patent: 6775795 (2004-08-01), Doll et al.
patent: 6794678 (2004-09-01), Hasegawa et al.
patent: 2003/0217313 (2003-11-01), Pfeiffer et al.
patent: 10007177 (2001-09-01), None
patent: WO 02/25296 (2002-03-01), None
“Design, modeling and simulation methodology for source synchoronousDDR memory subsystems” by Pham et al. Electronic Components and Technology Conference, 2000. 2000 Proceedings. 50thPublication Date: 2000 On pp. 267-271 Meeting Date: May 21, 2000-May 24, 2000 ISBN: 0-7803-5908-9 INSPEC Accession No. 6691302.
Mysliwitz Daniel
Schramm Achim
Britt Cynthia
Infineon - Technologies AG
Patterson & Sheridan L.L.P.
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