Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
1999-01-14
2001-12-04
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C710S008000, C710S012000, C710S100000, C710S104000, C710S120000, C710S120000, C711S154000, C326S037000
Reexamination Certificate
active
06327632
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of integrated circuits. More specifically, the present invention relates to the art of controlling input/output (I/O) of an integrated circuit, which applies equally to controlling I/O of a functional block of an integrated circuit of an embedded design type.
2. Background Information
All integrated circuits (or chips) have I/O pins to facilitate input and output of data values. Typically, the functional purposes of the I/O pins of a chip are defined, and combinatorial logic are employed to effectuate the functional behavior of the I/O pins. This prior art approach of employing combinatorial logic to control the I/O pins of a chip suffers from a number of disadvantages, including:
1. a large portion of the real estate of the chip being taken up by the I/O pin control combinatorial logic, and
2. the combinatorial logic must be redesigned for those I/O pins redefined with different functional purposes for different variants of the chip.
Thus, a more flexible or adaptable approach to controlling I/O of a chip is desired.
The above description including the disadvantages applies equally to functional blocks of integrated circuits that are of the embedded design type, where the functional blocks are inter-coupled by coupling the I/O signals of the functional blocks to on-chip buses, as if the functional blocks are physically different chips and the I/O signal lines are “I/O pins”. Thus, a more flexible or adaptable approach to controlling I/O of a functional block of a chip is also desired.
As will be disclosed in more detail below, the present invention provides a more flexible and adaptable approach as desired. From the description to follow, these and other advantages will be apparent to those skilled in the art. In the description to follow, the term “I/O pin” is intended to include the emerging usage and meaning of the term, i.e. internal interface signal lines that are configured and managed as if they are external interface signal lines, as well as the historical usage and meaning of the term.
SUMMARY OF THE INVENTION
A pin control unit and a plurality of addressable storage locations are provided to an integrated circuit to control either the I/O pins of a functional block of the integrated circuit or the I/O pins of the integrated circuit. Multiple ones of the addressable storage locations are correspondingly coupled to I/O buffers associated with the I/O pins. The pin control unit selectively loads bit values into appropriate ones of the addressable storage locations. In response, the I/O buffers input bit values from and/or output bit values to the corresponding I/O pins.
In one embodiment, three addressable storage locations are employed for each I/O pin, one for the associated input buffer, and two for the pull-up and pull-down devices of the associated output buffer. Additionally, the pin control unit controls various subsets of the I/O pins in a coordinated manner to operate them as I/O ports. A port bus is provided for each I/O port to supply output data values to the addressable storage locations provided, and each I/O port is provided with a port register. The I/O port register and various temporary storage elements are coupled to the port buses to facilitate data movement between these elements and the I/O ports.
In one embodiment where the “external” bus is a multiplexed address/data bus, the pin control unit employs a pair of I/O ports to output an instruction fetch address, and one of the pair of I/O ports to receive the instruction fetched. Additionally, the pin control unit employs the pair of the I/O ports to output and input data values. The pin control unit also employs the pair of the I/O ports to perform general purpose I/O in a manner that is compliant with particular architectural requirements.
In one embodiment, the addressable storage locations provided for the input and output buffers associated with the I/O pins, the I/O port registers and various temporary storage elements are all disposed in a common storage structure. In one embodiment, the common storage structure is a cache memory.
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Blakely & Sokoloff, Taylor & Zafman
Brecis Communications
Lee Thomas
Nguyen Tahn Q
LandOfFree
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