Adaptable datapath for a digital processing system

Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output addressing

Reexamination Certificate

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Details

C710S002000, C712S033000, C712S201000

Reexamination Certificate

active

07606943

ABSTRACT:
The present invention includes a adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., discrete cosine transform (DCT), fast-Fourier transform (FFT) and other operations. Other features are provided.

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