Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-24
2007-07-24
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10971609
ABSTRACT:
Techniques for increasing flexibility in use of virtual component blocks include a method for hardening a foundation block, a pin-unscrambling methodology for semi-hardened virtual component blocks, and parameterizable virtual component blocks. A method for hardening a foundation block and utilizing it in a circuit design comprises the steps of defining a virtual component foundation block, hardening an interior region of the foundation block including at least the critical timing components such as the system bus. The foundation block has a “soft collar” for allowing interface parameters to be specified when the foundation block is incorporated into a circuit design. In addition, the foundation block may comprise an internal, hierarchical clocking scheme for even clock distribution and optimum performance. For example, all internal clock delays may be padded, except the longest one, so that the clock signal arrives at all relevant reference points within the foundation block at the same time.
REFERENCES:
patent: 4354268 (1982-10-01), Michel et al.
patent: 4872169 (1989-10-01), Whetsel, Jr.
patent: 5537652 (1996-07-01), Friedl et al.
patent: 5557779 (1996-09-01), Minami
patent: 5577213 (1996-11-01), Avery et al.
patent: 5581669 (1996-12-01), Voth
patent: 5644754 (1997-07-01), Weber et al.
patent: 5701309 (1997-12-01), Gearhardt et al.
patent: 5737234 (1998-04-01), Seidel et al.
patent: 5761078 (1998-06-01), Fuller et al.
patent: 5774371 (1998-06-01), Kawakami
patent: 5794014 (1998-08-01), Shetty et al.
patent: 5838583 (1998-11-01), Varadarajan et al.
patent: 5960186 (1999-09-01), Jones et al.
patent: 5983303 (1999-11-01), Sheafor et al.
patent: 6034542 (2000-03-01), Ridgeway
patent: 6058253 (2000-05-01), Lowe
patent: 6102961 (2000-08-01), Lee et al.
patent: 6134606 (2000-10-01), Anderson et al.
patent: 6148432 (2000-11-01), Brown
patent: 6154873 (2000-11-01), Takahashi
patent: 6237128 (2001-05-01), Folberth et al.
patent: 6260175 (2001-07-01), Basel
patent: 6269467 (2001-07-01), Chang et al.
patent: 6286128 (2001-09-01), Pileggi et al.
patent: 6292929 (2001-09-01), Scepanovic et al.
patent: 6305001 (2001-10-01), Graef
patent: 6311302 (2001-10-01), Cassetti et al.
patent: 6311313 (2001-10-01), Camporese et al.
patent: 6327696 (2001-12-01), Mahajan
patent: 6347395 (2002-02-01), Payne et al.
patent: 6367051 (2002-04-01), Pileggi et al.
patent: 6367060 (2002-04-01), Cheng et al.
patent: 6910195 (2005-06-01), Akkiraju
patent: 0 466 939 (1992-01-01), None
patent: 2 326 065 (1998-12-01), None
Chao, Ting-Hai et al., “A Clock Net Routing Algorithm For High-Performance VLSI”,IEEE1992, pp. 343-347.
Jackson, Michael A.B. et al., “Clock Routing For High Performance ICs”, 27thACM/IEEE Design Automation Conference1990, pp. 573-579.
Khan, Wasim et al., “An Hierarchical Approach to Clock Routing in High Performance Systems”,IEEE1994, pp. 467-470.
Sato, Hidenori et al., “A Balanced-Mesh Clock Routing Technique Using Circuit Partitioning”,IEEE1996, pp. 237-243.
Su, Hsiao-Pin et al., “A Timing-Driven Soft-Macro Placement and Resynthesis Method In Interaction With Chip Floorplanning”;IEEE Transactions on Computer-Aided Design Of Integrated Circuits and Systems; Apr. 1999; vol. 18, No. 4; pp. 475-483.
“Virtual Socket Interface Alliance (VSIA)”, VCI Standard OCB 2, Ver. 1.0 Dec. 9, 1999, pp. 57.
International Search Report, PCT/US01/01738, May 1, 2001.
International Search Report, PCT/US01/20641, Jun. 28, 2001.
International Search Report, PCT/US01/01820, Apr. 18, 2001.
Cooke Laurence H.
Venkatramani Kumar
Bingham & McCutchen LLP
Cadence Design Systems Inc.
Chiang Jack
Tat Binh
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