Active voltage level bus switch (or pass gate) translator

Details Active voltage level bus switch (or pass gate) translator Active voltage level bus switch (or pass gate) translator

2002-11-21

2004-08-24

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S083000, C326S121000, C326S068000, C327S112000, C327S333000

Reexamination Certificate

active

06781415

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present application relates to bus switches and more particularly to bus switches that also translate from one voltage to another.
2. Background Information
Microprocessors and application specific integrated circuits and other such large scale integrated circuits often communication off chip via solid state switches, called bus switches. Due to the variety of circuit types available, e.g. TTL, LVTTL (also known as LVLS—low level logic signal), and even ECL, voltage translation is often combined or required in such bus switches.
FIG. 1
shows a known bus switch
2
that couples a high voltage node
4
to a low voltage node
6
. The gate
8
of the bus switch
2
is driven by a PMOS
10
and an NMOS
12
in a push/pull arrangement. The source
14
of the PMOS is connected via a diode
16
to Vcc. The gates of the PMOS
10
and the NMOS
12
are joined as a low true enable
18
. When the enable signal
18
is high, the NMOS
12
is on and the PMOS
10
is off. In this state the gate
8
of the bus switch
2
is low thereby keeping the NMOS bus switch
2
off and isolating the node
4
from the node
6
. When the signal
18
is low, the NMOS
12
is off, the PMOS
10
is on and the P-rail voltage appears at the gate
8
of the bus switch
2
turning it on connecting nodes
4
and
6
. The design parameters of the bus switch
2
, with the p-rail voltage at its gate, clamps the highest voltage at the low voltage node
6
when the bus switch is on. In other instances, a reference voltage may be applied to the p-rail, and the clamped voltage at the low voltage node
6
can be programmed by changing the reference voltage. The PMOS
10
, NMOS
12
arrangement with a single output and input is a logical inverter with a threshold defined by the structural parameters of the MOSFETs, as is known in the art. For example, the threshold for the PMOS
10
, NMOS
12
circuit may be set to about +2.5 volts.
Other translation transceivers are known in the art that pass signals in both directions, but these circuits require a direction signal. The direction input enables the translation switch to pass the signal in a particular direction.
There is a need for a bi-directional bus switch that translates voltage from high to low and from low to high and operates in either direction without needing a direction signal.
SUMMARY
The present invention provides a bi-directional voltage level translating switch that dispenses with a direction signal. The voltage level translating switch includes an NMOS device with the drain connected to higher voltage circuitry and the source to lower voltage level circuitry, although the voltages may be about equal in some applications.
An enable signal via control circuitry drives the gate of the NMOS device turning it on or off. The voltage level supplied by the control circuitry to the gate clamps or limits the voltage level on the source to some voltage that is compatible with the lower voltage circuitry regardless of the voltage on the drain.
Pull up circuit is connected to the drain of the NMOS switch, and provides a connection to the higher voltage supply. A threshold is established for the pull up circuitry that is lower than the lower voltage signal level. When the switch is on and the lower voltage circuitry drives the drain higher beyond the threshold, the pull up circuitry activates and drives the drain to the higher voltage. Again, the source is clamped via the gate control circuitry. When the drain is driven lower beyond the threshold the pull up circuitry is disabled. When the translation switch is on and a lower voltage circuit drives the drain low via an on translation switch, the pull up circuitry is designed so that the lower voltage drive circuit overcomes the pull up circuit capability to drive the drain high. Similarly the higher voltage drive circuitry will overcome the pull up circuits ability to drive the drain high.
Pull up circuitry may be connected to the source of the NMOS transistor to improve its speed. The circuitry will be similar to the pull up circuitry connected to the drain, but connected between the source and the Vccl—the low voltage power supply.
The ability of the higher and lower drive circuitry to drive low and overcome the pull up circuits, can be achieved through the design of a MOS transistor switch in a preferred embodiment of the pull up circuitry. The physical size of that MOS switch can be made small enough, as known in the art, to be overcome by the drive circuits.
In another preferred embodiment, the pull up circuits may include a low impedance path to the higher voltage supply, but that low impedance path is designed to exist for-a given time and then a higher impedance path is provided. The higher impedance path is designed to be overcome and driven low by the drive circuitry connected to either side of the switch.


REFERENCES:
patent: 5381062 (1995-01-01), Morris
patent: 5751168 (1998-05-01), Speed, III et al.
patent: 5926056 (1999-07-01), Morris et al.
patent: 6005432 (1999-12-01), Guo et al.
patent: 6114876 (2000-09-01), Kwong et al.
patent: 6188243 (2001-02-01), Liu et al.
patent: 6504418 (2003-01-01), Coughlin, Jr.
Notification of Transmittal of the International Search Report or the Declaration, Dated Apr. 10, 2003.

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