Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-20
2002-05-28
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S297000, C438S439000
Reexamination Certificate
active
06396113
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to an element isolating structure of the semiconductor device.
2. Description of the Background Art
In a semiconductor device, individual semiconductor elements are electrically isolated by LOCOS isolation or trench isolation. In the case where an integration degree of the semiconductor device is relatively low, the LOCOS isolation is enough. However, the trench isolation has been increasingly required with an enhancement in the integration degree.
An example of a structure of the trench isolation will be described with reference to FIG.
25
. In
FIG. 25
, a plurality of MOS transistors are formed on a P-type silicon substrate
61
, a trench is provided on the silicon substrate
61
between the MOS transistors in order to electrically isolate the individual MOS transistors, and a silicon oxide
66
formed by CVD (chemical vapor deposition) is buried in the trench to form a trench portion
65
.
An N-type source-drain layer
62
constituting the MOS transistor is provided in a surface of the silicon substrate
61
on both sides of the trench portion
65
, a gate oxide film
63
is provided to cover the trench portion
65
and the source-drain layer
62
, and a gate electrode
64
is provided from the source-drain layer
62
to a channel region.
During an operation of the MOS transistor, a depletion layer covering the source-drain layer
62
also extends to the trench portion
65
side as well as the channel region side. By the existence of the trench portion
65
, it is possible to prevent a punch through from being generated between the source-drain layers
62
on both sides of the trench portion
65
.
However, when the microfabrication of the semiconductor device is improved to obtain a design rule of 0.15 &mgr;m or less, a spacing between elements is reduced and the depletion layers extending from the source-drain layers
62
on both sides of the trench portion
65
shown in
FIG. 25
approach each other beyond a bottom of the trench portion
65
so that a punch-through is generated between the source-drain layers
62
to easily cause a current leakage.
In order to avoid such a situation, a depth of the trench should be increased to inhibit the depletion layers from coming in contact with each other and a P-type diffusion layer having a high concentration should be provided on the outer periphery of the bottom surface of the trench portion to suppress the extension of the depletion layers. However, if the depth of the trench is increased, there is a possibility that an insulator might be buried therein with difficulty or a crystal defect might be generated in the silicon substrate due to a stress generated with the formation of the trench.
Moreover, in the case where the P-type diffusion layer is provided on the outer periphery of the bottom surface of the trench portion, an electric field in the depletion layer is increased depending on the concentration of a P-type impurity so that a junction leakage is increased by an electron trap assist tunneling phenomenon in which carriers are excited to a conduction band through a defect state in some cases.
In the structure described with reference to
FIG. 25
, furthermore, a positive charge is induced into the silicon oxide
66
and a negative charge is induced into the silicon substrate
61
in the vicinity of an interface between the silicon oxide
66
of the trench portion
65
and the silicon substrate
61
and a channel (a so-called side channel) using the silicon oxide
66
as a gate oxide film is generated to form a parasitic MOS transistor, resulting in the generation of a leakage current.
In the MOS transistor formed on the P-type silicon substrate, there has been known the fact that a leakage current generated between the source-drain layers with a gate voltage set to a ground level is decreased when a threshold voltage is increased. In order to raise the threshold voltage, it is preferable that a substance having a great electron affinity should be used as a gate material. This is the same as in the above-mentioned parasitic MOS transistor. By burying the substance having a great electron affinity in the silicon oxide
66
of the trench portion
65
, a threshold voltage of the parasitic MOS transistor can be raised to reduce a leakage current.
As means for preventing the leakage current from being caused by a punch-through, a structure in which an electric conductor is buried in a trench portion has been proposed in addition to the above-mentioned means.
An example of a structure implementing the preventing means is illustrated in FIG.
26
. Such a structure has been disclosed in Japanese Patent Application Laid-Open No. P01-138730A (1989), for example. In
FIG. 26
, a trench portion
55
is provided in place of the trench portion
65
shown in FIG.
25
. The trench portion
55
is constituted by a silicon oxide film
56
provided on an inner surface of a trench, a compensating material layer
57
provided on an inner surface of the silicon oxide film
56
, and an insulator
58
provided in a space defined by the compensating material layer
57
. Other structures are the same as those in FIG.
25
.
The compensating material layer
57
serves to compensate for a negative charge in a silicon substrate
61
. As the compensating material layer
57
are used a substance having a great electron affinity, for example, a polysilicon layer doped with boron (B), aluminum (Al) or the like, a silicide layer such as a titanium silicide (TiSi) layer, a tungsten silicide (WSi) layer or the like, or a layer made of a refractory metal such as titanium (Ti), molybdenum (Mo) or the like.
In the structure shown in
FIG. 26
, however, there is a problem in that the compensating material layer
57
in the trench portion
55
is kept in a floating state, the amount of electric charges present in the compensating material layer
57
is varied depending on a manufacturing situation and a leakage current is reduced with difficulty.
The compensating material layer
57
is introduced to act as a substance to have a small work function difference between the silicon substrate
61
and the insulator
58
, in other words, serves to change the characteristics of a material to fill in the trench. Accordingly, the compensating material layer
57
should be used in the floating state. However, the floating state sometimes causes electric charges to be stored in the process of manufacturing the semiconductor device such as ion implantation. Moreover, it is also supposed that the amount of electric charges is not constant and might cause a leakage current to be generated.
FIG. 27
also illustrates a structure in which an electric conductor is buried in a trench portion. The structure shown in
FIG. 27
has been disclosed in Japanese Patent Application Laid-Open No. P08-172124A (1996), for example. An insulating film
77
is provided on an inner wall surface of a trench
72
formed in a semiconductor substrate
71
, and a conductive film
78
is provided on an inner wall surface of the insulating film
77
and a bottom of the trench
72
and is in contact with the semiconductor substrate
71
at the bottom.
Moreover, an insulating film
79
is buried in a space defined by the conductive film
78
, and an insulating film
74
is provided over the trench
72
to protrude therefrom.
In the structure shown in
FIG. 27
, if an electric potential of the conductive film
78
is to be fixed, it is necessary to control the electric potential of the conductive film
78
according to an electric potential of an N-type semiconductor region (not shown) present on both sides of the trench
72
. However, it is hard to control the electric potential of the conductive film
78
.
More specifically, in the case where an electric potential of the semiconductor substrate
71
is set to 0 V, a current does not flow between the conductive film
78
and the semiconductor substrate
71
if the electric potential of the conductive film
78
is also se
Fujinaga Masato
Kunikiyo Tatsuya
Flynn Nathan
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Wilson Scott R.
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