Active trace debugging for hardware description languages

Details Active trace debugging for hardware description languages Active trace debugging for hardware description languages

2001-01-19

2003-04-08

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C703S014000

Reexamination Certificate

active

06546526

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to debugging hardware description language (HDL) code. Specifically, the present invention discloses a system and method that utilizes an active code tracing strategy to help a user locate faulty circuit designs.
2. Description of the Prior Art
With the gate counts and system complexity of circuit designs growing exponentially, engineers are spending more and more time on functional debugging. Debugging is now recognized as a critical step in the entire design and compilation process of complex circuitry. Indeed, the cost of debugging often dominates all other design expenses.
Hardware description languages (HDLs) are used to describe and model complex circuits, as debugging HDL code is considerably more efficient than the traditional methods of circuit schematics or in-circuit emulators. To date, however, it is the software industry that has presented the most comprehensive treatment of debugging. Little has been done in the hardware domain to address the debugging of ASICs and processors, even though such systems can be in excess of 10 million gates, and have correspondingly complex HDL code.
Engineers typically use HDL code to run simulations on a circuit design. Simulation results are compared to the design specifications to find any deviations. If any such deviations are found, the engineer must manually trace through the HDL source code to find the offending code that is responsible for the design flaw. This debugging process can be very difficult and tedious, especially if the engineer doing the debugging did not design the circuit. Although detecting the source of bugs is of critical importance, few methods have been proposed to assist an engineer in this task.
One of the simplest and most common methods for finding bugs is tracing. Please refer to FIG.
1
and FIG.
2
.
FIG. 1
is a diagram of a portion of a circuit
10
. The diagram is presented to a user on a computer display as part of an HDL design package, and is a graphical representation of HDL source code that describes the circuit
10
.
FIG. 2
shows sample HDL source code for the circuit portion
10
of FIG.
1
.
A circuit simulator (not shown) uses the portion of HDL source code
20
, and a great deal of other code as well, to generate circuit timing data. In particular, the simulator will yield timing data for the circuit portion
10
. By studying the timing data, an engineer may learn that the signal line n_dout
1
12
goes into an improper state at a certain time. The engineer can click on the circuit portion
10
, and the HDL design package will present the source code
20
in a different window on the display. To find the bug that is causing n_dout
1
12
to go into an improper state, it is logical that the engineer exhaustively check every line of code that sets n_dout
1
12
. This is termed tracing. For example, if at a circuit execution time t=45, n_dout
1
12
is equal to ALU
16
, then, for the code
20
, the engineer would know that line
22
is the line of code responsible for the state of n_dout
1
12
at t=45. The engineer
30
must then determine if mux_sel
14
has an incorrect value of “011” at t=45, or if setting n_dout
1
12
equal to ALU
16
is incorrect.
Although tracing in the tiny code fragment
20
is quite straightforward, the fact is that, in most circuit designs, hundreds of lines of code may be responsible for setting the state of n_dout
1
12
. That is, the line n_dout
1
12
may be driven by many different signal lines at any given time, and hence there will be many different lines of source code that assign an assignment state to the element variable “n_dout
1
”
24
. These lines of assignment can be scattered throughout the source code. Worse still, many of them may be identical. For example, there may be several lines of source code that state, ‘n_dout
1
=ALU’. It is up to the engineer to parse the nested structures of the source code to determine which line is actually responsible for setting the value of “n_dout
1
”
24
, and thus the state of signal line n_dout
1
12
. In any sufficiently complex circuit design, this process can turn into an enormously tedious and time-consuming task.
SUMMARY OF THE INVENTION
It is therefore a primary objective of this invention to provide a method and system for performing an active trace function to assist in finding lines of source code that are responsible for the state of a signal at a certain execution time.
The present invention, briefly summarized, discloses a method and corresponding system for assisting with debugging hardware description language (HDL) code in a debugger on a computer system. The HDL code is used to describe a circuit. Circuit simulation data is obtained for the circuit, the simulation data being generated according to the HDL code. A circuit execution time is selected, and the simulation data should at least span the circuit execution time. A debugging element is selected, which is a circuit element in the circuit having a debugging state at the circuit execution time according to the simulation data. A target line of HDL code is then presented to a user. The target line of HDL code is the line of code responsible for setting the debugging element into the debugging state at the circuit execution time.
It is an advantage of the present invention that by presenting the target line of HDL source code, an engineer can more quickly trace and track down bugs in the HDL source code that describes a circuit. Overall debugging time requirements are therefore reduced.


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patent: 6389586 (2002-05-01), McElvain
patent: 6421251 (2002-07-01), Lin
patent: 6305009 (2002-10-01), Goor
Kadrovach et al, “Hardware Simulation Eith Software Modeling for Enhanced Architecure Performance Analysis,” IEEE, 1998, pp. 454-461.*
Hartley et al, “A Synthesis, Test and Debug Environment for Rapid Prototyping of DSP Designs,” IEEE, 1991, pp. 205-214.*
Vranken et al, “Debug Facilities in the Trimedia CPU64 Architecture,” IEEE, May 1999, pp. 1-6.*
Vermeulen et al, “Silicon Debug of a Co-Processor Array for Video Applications,” IEEE, Nov. 2000, pp. 47-52.

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