Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2001-04-17
2003-04-01
Lee, Michael G. (Department: 2876)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S026000, C326S027000, C326S083000, C326S086000
Reexamination Certificate
active
06541998
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for active termination devices generally and, more particularly, to a method and/or architecture for active termination devices with an enable/disable feature.
BACKGROUND OF THE INVENTION
Transmission line effects are well known. An unterminated transmission line at a receiving end will momentarily experience approximately twice the voltage at the unterminated end as is presented by a source driver at the transmitting end. The excess voltage then reflects from the receiving end and propagates back down the transmission line toward the source driver. To prevent this doubling of the voltage, transmission lines are commonly terminated with a passive termination device having an impedance that substantially matches that of the transmission line. For example, if the transmission line has an impedance of 50 ohms, the passive termination device will be a 50-ohm resistor.
Referring to
FIG. 1
, a passive termination device at the receiving end
100
of an ideal transmission line
102
is shown. Here, two resistors (i.e., R
1
and R
2
) present a small signal impedance of Z
0
to the ideal transmission line
102
to prevent reflections. Referring to
FIG. 2
, another passive termination device at the transmitting end
104
of the ideal transmission line
102
is shown. Here, a single resistor (i.e., R
1
) is provided in series with the source driver
106
to absorb reflections created by an unterminated receiving end
108
.
Most types of circuits are susceptible to transmission line effects. For example, transmission line effects occur in the telecommunications transmissions over a wire line path, in computer networks over an Ethernet or other interconnecting means, and within the computer system itself. In each of these circuits, the transmission line is terminated with an impedance that substantially matches the impedance of the transmission line to prevent the doubling of the original signal. In many applications, where power consumption is a critical issue, the use of a passive termination device (i.e., a resistor) consumes excessive power. The power consumed by an active termination element, which may be a transistor, can be reduced in comparison to that of the passive, or resistive, termination element.
SUMMARY OF THE INVENTION
The present invention concerns a termination circuit for use on a conductor of a transmission line. The termination circuit generally comprises a first, second, third, and fourth transistor. The first transistor may have (i) a first drain node couplable to the conductor, (ii) a first source node couplable to a first power source presenting a first reference voltage, and (iii) a first gate node. The second transistor may have (i) a second drain node couplable to the conductor, (ii) a second source node couplable to a second power source presenting a second reference voltage, and (iii) a second gate node. The third transistor (i) may have a third source node coupled to the first gate node and (ii) may be configured to bias the first gate node to a first voltage below the first reference voltage. The fourth transistor (i) may have a fourth source node coupled to the second gate node and (ii) may be configured to bias the second gate node to a second voltage above the second reference voltage.
The objects, features and advantages of the present invention include providing a method and/or architecture for active termination devices with an enable/disable feature that (i) result in low power consumption, (ii) are simple in design, (iii) are easily incorporated into existing designs without major changes, and/or (iv) have a termination function that may be controllably enabled/disabled.
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“Termination Techniques for High-Speed Buses”, By Karthik Ethirajan and John Nemec, EDN Magazine, Feb. 16, 1998, Issue 04, 9 pages.
Manapat Rajesh
Srinivasagam P. Kannan
Cypress Semiconductor Corp.
Lee Michael G.
Maiorana P.C. Christopher P.
Paik Steven S.
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