Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2003-02-26
2004-03-23
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C710S100000, C710S015000
Reexamination Certificate
active
06711073
ABSTRACT:
TECHNICAL FIELD
The invention relates to integrated circuits, and, more particularly, to a method and circuit for efficiently controlling the input impedance of externally accessible integrated circuit terminals.
BACKGROUND OF THE INVENTION
Integrated circuits receive signals through externally accessible input terminals of various designs. In some integrated circuits, the magnitude of the input impedance of input terminals is not critical. Other integrated circuits, particularly memory devices operating at a high speed, the input impedance of at least some of the input terminal must be controlled for optimum performance.
FIG. 1
illustrates a conventional memory device that can advantageously use one or more embodiments of the active termination circuit in according to the present invention. The memory device shown in
FIG. 1
is a synchronous dynamic random access memory (“SDRAM”)
10
, although the active termination circuit may also be used in other memory devices and other integrated circuits. The SDRAM
10
includes an address register
12
that receives either a row address or a column address on an address bus
14
through an address input buffer
16
. The address bus
14
is generally coupled to a memory controller (not shown). Typically, a row address is initially received by the address register
12
and applied to a row address multiplexer
18
. The row address multiplexer
18
couples the row address to a number of components associated with either of two memory banks
20
,
22
depending upon the state of a bank address bit forming part of the row address. Associated with each of the memory banks
20
,
22
is a respective row address latch
26
, which stores the row address, and a row decoder
28
, which applies various signals to its respective memory bank
20
or
22
as a function of the stored row address. The row address multiplexer
18
also couples row addresses to the row address latches
26
to refresh memory cells in the memory banks
20
,
22
. The row addresses are generated for refresh purposes by a refresh counter
30
that is controlled by a refresh controller
32
.
After the row address has been applied to the address register
12
and stored in one of the row address latches
26
, a column address is applied to the address register
12
. The address register
12
couples the column address to a column address latch
40
. Depending on the operating mode of the SDRAM
10
, the column address is either coupled through a burst counter
42
to a column address buffer
44
, or to the burst counter
42
which applies a sequence of column addresses to the column address buffer
44
starting at the column address that is output by the address register
12
. In either case, the column address buffer
44
supplies a column address to a column decoder
48
which applies various column signals to respective sense amplifiers and associated column circuitry
50
,
52
for the respective memory banks
20
,
22
.
Data to be read from one of the memory banks
20
,
22
are coupled to the column circuitry
50
,
52
for one of the memory banks
20
,
22
, respectively. The data are then coupled to a data output register
56
which applies the data to a data bus
58
through a data input buffer
59
and a data output buffer
60
. Data to be written to one of the memory banks
20
,
22
are coupled from the data bus
58
through a data input register
62
to the column circuitry
50
,
52
and then are transferred through word line driver circuits in the column circuitry
50
,
52
to one of the memory banks
20
,
22
, respectively. A mask register
64
may be used to selectively alter the flow of data into and out of the column circuitry
50
,
52
, such as by selectively masking data to be read from the memory banks
20
,
22
.
The above-described operation of the SDRAM
10
is controlled by a command decoder
68
responsive to high level command signals received on a control bus
70
and coupled to the command decoder through a command input buffer
72
. These high level command signals, which are typically generated by a memory controller (not shown in FIG.
1
), are a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a column address strobe signal CAS*, and a row address strobe signal RAS*, with the “*” designating the signal as active low or complement. The command decoder
68
generates a sequence of command signals responsive to the high level command signals to carry out the function (e.g., a read or a write) designated by each of the high level command signals. These command signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted
Each of the input buffers
16
,
59
,
72
includes a respective termination circuit
90
that is coupled to a respective externally accessible input terminal and that determines the input impedance of the input buffer. Conventional termination circuits
90
include, for example, resistors as well as NMOS and PMOS transistors that are biased to an ON condition. In the past, it has been difficult to efficiently control the input impedance of the input terminals. The resistance provided by transistors and other components can vary with process variations and operating temperature, thus making it difficult to precisely control input impedance. Process variations can be compensated for to some extent by altering the circuit topography during manufacturer using fusible links and the like. However, compensating for processing variations in this manner increases the number of components included in the termination circuit and may increase the number of manufacturing steps. Furthermore, compensating for process variations in does not compensate for temperature variations. Therefore, the input impedance can vary with changes in temperature. Another problem with conventional termination circuits using PMOS or NMOS transistors is that the effective impedance of the transistor varies with the source-to-drain voltage, thus making the impedance of the transistor sensitive to variations in the supply voltage.
A relatively complex circuit (not shown) can be used to implement an active termination circuit
90
that precisely controls the input impedance. However, providing a relatively complex termination circuit
90
for each of the many input terminals of a conventional integrated circuit, such as the SDRAM
10
, greatly increases the amount of circuitry in the integrated circuit.
There is therefore a need for a circuit and method that uses relatively little circuitry and yet is able to precisely control the input impedance of an input terminal despite process, temperature and supply voltage variations.
SUMMARY OF THE INVENTION
An active termination circuit and method controls the input impedance of a plurality of externally accessible input terminals in an integrated circuit, such as a memory device. Each of the externally accessible input terminals are coupled to a respective first variable impedance device and a respective second variable impedance device. The impedance of one of the first variable impedance devices is compared to a first predetermined impedance by suitable means, such as by deriving a feedback signal from a voltage divider formed by the first variable impedance device and the first predetermined impedance. Similarly, the impedance of one of the second variable impedance devices is compared to a second predetermined impedance by suitable means, such as by deriving a feedback signal from a voltage divider formed by the second variable impedance device and the second predetermined impedance. Based on these comparisons, the impedances of all of the first variable impedance devices and all of the second variable impedance devices are adjusted. More specifically, the impedances of all of the first variable impedance device are adjusted so that they have a predetermined relationship to the first predetermined impedance, and the impedances of a
Dorsey & Whitney LLP
Nguyen Thinh T
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