Active photodiode CMOS image sensor structure

Details Active photodiode CMOS image sensor structure Active photodiode CMOS image sensor structure

2000-06-26

2002-09-10

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S293000, C257S229000, C257S232000, C257S233000

Reexamination Certificate

active

06448595

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an image sensor structure and method of manufacture. More particularly, the present invention relates to an active photodiode CMOS image sensor structure and method of manufacture.
2. Description of Related Art
Photodiode image sensor is currently a common type of image sensing device. Typically, a photodiode image sensor includes a reset transistor and a light-sensing region formed by diodes. Each photodiodes is formed by joining an n-doped region with a p-doped body (n
+
/p junction). During operation, a voltage is applied to the gate terminal of the reset transistor so that the reset transistor is switched on and the capacitor at the n
+
/p diode junction is charged up. When the diode is charged to a certain potential level, the reset transistor is switched off so that the n
+
/p diode is reverse biased leading to the formation of a depletion region. Electron/hole pairs are generated when light shines on the light-sensitive n
+
/p region. The electrons and the holes are sorted out by the electric field within the depletion region. The electrons migrate towards the n-doped region so that electric potential in the n-doped region will drop. On the other hand, the holes move away from the depletion region towards the p-doped body. Ultimately, the holes are channel away. If the electrons in the n-doped region are transferred by a transistor to a bus line, electric charges produced by photons can be read from an output terminal without going through any amplification. This type of photosensitive device is called passive pixel photodiode. However, if the n-doped region is connected to a source follower formed from a transfer transistor, the source follower is able to supply a large enough current to stabilize the voltage at the output terminal and reduce noises. This type of low noise photosensitive device is often called active pixel photodiode.
In recent years, active photodiode CMOS image sensor has been used in some low-end image sensing equipment as a replacement for high cost charge couple device (CDD). In fact, active photodiode CMOS image sensor has high quantum efficiency, low read-out noises, high dynamic range and random access property. Moreover, the active photodiode CMOS image sensor is a hundred percent compatibility with other CMOS devices. Hence, the image sensor can easily integrate with other control circuits, analogue to digital (A/D) converters and digital signal processors to form a system on a silicon chip (so-called system on a chip).
FIG. 1
is a schematic cross-sectional view of a conventional active photodiode CMOS image sensor. To form the conventional active photodiode CMOS image sensor shown in
FIG. 1
, several steps are required. First, a substrate
100
is provided, and then an isolation region
102
is formed on the substrate
100
. An oxide layer and a polysilicon layer are formed over the substrate
100
. Photolithographic and etching processes are carried out to pattern the oxide layer and the polysilicon layer to form the gate oxide layer
104
and the polysilicon gate
106
of a reset transistor
120
. Using the isolation region
102
and the polysilicon gate
106
as a mask, an ion implantation and a thermal drive-in operation are sequentially carried out. Ultimately, doped regions
112
are formed in source/drain regions
108
and photodiode sensing regions
110
. Spacers
114
are next formed over the sidewalls of the polysilicon gate
106
and the gate oxide layer
104
.
In general, a self-aligned silicide (Salicide) process is included in the manufacturing of a CMOS transistor for depositing a silicide layer over polysilicon gate terminals
106
and source/drain terminals
108
so that electrical resistance at those terminals are reduced.
However, in the manufacturing of active photodiode CMOS image sensor, the self-aligned silicide process will deposit a silicide layer over the light-sensitive photodiode region
110
in addition to the polysilicon gate
106
and the source/drain terminal
108
. The addition of a silicide layer over the light-sensitive photodiode region
110
will increase the amount of back reflections of the incoming light resulting in a considerable reduction in photoelectric conversion and lowering of sensor sensitivity.
In addition, the interface state of the surface the photodiode sensor region
110
contains numerous defects. When light impinges upon the n
+
/p light-sensitive photodiode region
110
, electron/hole pairs are produced. However, the separation of electrons and holes by the electric field in the depletion region will be affected by defects in the interface states leading to a relatively large surface leakage of current.
SUMMARY OF THE INVENTION
Accordingly, the purpose of the present invention is to provide an active photodiode CMOS image sensor structure capable of increasing photoelectric conversion rate so that overall sensitivity of the sensor improves.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides an active photodiode CMOS image sensor structure. The sensor includes a light-sensitive photodiode region, a transistor and a cap layer. The light-sensitive photodiode region is buried within a substrate body. The transistor is formed over the substrate body. The source region of the transistor is connected to a portion of the light-sensitive photodiode region. The cap layer is formed as a gate dielectric layer above the light-sensitive photodiode region.
This invention also provides a method of forming the active photodiode CMOS image sensor. A gate dielectric layer, a gate conductive layer and a cap layer are sequentially formed over a substrate body. Photolithographic and etching techniques are employed to pattern the gate dielectric layer, the gate conductive layer and the cap layer into a gate structure. An ion implantation is carried out followed by a thermal drive-in operation so that doped source/drain regions and doped light-sensitive photodiode regions are formed. A cover layer is formed over the exposed substrate body. Thereafter, a portion of the cover layer is removed retaining a cover layer over the light-sensitive photodiode region. The cap layer is removed and then spacers are formed on the sidewalls of the gate structure. Finally, a self-aligned silicide process is carried out to form a silicide layer above the gate conductive layer and the source/drain regions.
By forming a cover layer over the light-sensitive photodiode region, no silicide layer is formed over the light-sensitive photodiode region after a self-aligned silicide process. In the absence of a light-reflecting silicide layer, the reflection of a large quantity light from the light-sensitive photodiode region is avoided.
In addition, the cover layer on top of the light-sensitive photodiode region is formed under similar conditions as forming the gate dielectric layer. Since the gate dielectric layer is an oxide layer formed by a quality process, the interface between the dielectric layer and the substrate body has few defects. With very little current leak from the surface of the light-sensitive regions, only a very small dark current flows in the sensing device.
Moreover, since the cover layer is formed in the thermal drive-in step for forming the source/drain region, only one more photomask-making step is required when compared with a standard CMOS manufacturing process.
Furthermore, the light-sensitive photodiode region has a lower dopant concentration than a conventional photodiode region. Consequently, a thicker depletion region is produced when a voltage is applied to the light-sensitive photodiode region. Ultimately, a higher photoelectric conversion rate can be obtained.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6023081 (2000

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