Active noise-canceling scheme for dynamic circuits

Details Active noise-canceling scheme for dynamic circuits Active noise-canceling scheme for dynamic circuits

2001-07-31

2003-06-03

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S024000

Reexamination Certificate

active

06573756

ABSTRACT:

BACKGROUND
High fan-in domino gates tend to be leaky and prone to noise. Examples of such gates are high fan-in dynamic NOR gates used in schedulers and register files. The inputs to these dynamic gates may traverse long distances running parallel to each other. A capacitive charge may develop between neighboring read-select lines, which may increase with the length of the wires, their height, and inversely to the distance between them.
The inter-wire coupling capacitance between the read-select lines may be a significant source of noise, and may affect the performance of the high fan-in domino gates. One technique for dealing with capacitive coupled noise in the circuit is to replace the leaky high fan-in domino gates with gates that include transistors with high threshold voltages (V
t
). However, the use of high V
t
devices may entail certain performance trade-offs.


REFERENCES:
patent: 5841300 (1998-11-01), Murabayashi et al.
patent: 6002272 (1999-12-01), Sonasekhar et al.
patent: 6404234 (2002-06-01), Hsu et al.
patent: 2002/0075038 (2002-06-01), Mathew et al.

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