Electric lamp and discharge devices: systems – Plural power supplies – Plural cathode and/or anode load device
Reexamination Certificate
2001-12-27
2004-12-28
Wong, Don (Department: 2821)
Electric lamp and discharge devices: systems
Plural power supplies
Plural cathode and/or anode load device
C345S076000, C313S500000, C438S487000
Reexamination Certificate
active
06836075
ABSTRACT:
This application claims the benefit of the Korean Application No. P.2000-085560 filed on Dec. 29, 2000, which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an active matrix organic electroluminescence display device, and more particularly, to an active matrix electroluminescence display device and a method for manufacturing the same by a sequential lateral solidification (SLS) method that can obtain greater uniformity of luminance and a packing density of an integrated circuit (IC) than a related art low temperature poly process.
2. Discussion of the Related Art
Recently, various display devices such as liquid crystal display (LCD) device, a plasma display panel (PDP) device, a field emission display (FED) device and an electroluminescence (EL) device have been studied with development of flat display devices. These flat display devices are classified into two types according to a driving method: a passive matrix method and an active matrix method. The passive matrix method requires current greater than the active matrix method.
Accordingly, in current driving methods of the FED and EL devices, it is regarded that the active matrix method is more efficient than the passive matrix method because the passive matrix method requires a greater current level than the active matrix method even though a line transmission time is equal.
FIG. 1
is an equivalent circuit diagram of a unit pixel in a related art two transistor (2T) active matrix organic electroluminescence display (OED) device.
As shown in
FIG. 1
, the related art active matrix organic electroluminescence display device includes a scan line
1
, a data line
2
, a power line
3
, an electroluminescence device
7
, a switching transistor
4
, a driving transistor
5
and a capacitor
6
.
At this time, the scan line
1
is formed in one direction, and then the data line
2
is formed perpendicular to the scan line
1
. The power line
3
is formed in parallel to the data line
2
at a distance from the data line
2
. The electroluminescence device
7
emits lights according to a voltage applied in a pixel region formed by the scan line
1
, the data line
2
and the power line
3
. The switching transistor
4
switches a signal of the data line
2
according to a signal of the scan line
1
. Subsequently, the driving transistor
5
applies a power supply of the power line to the electroluminescence device according to a signal applied through the switching transistor
4
. The capacitor
6
is formed between the power line
3
and a gate electrode of the driving transistor
5
.
A structure of the unit pixel in the related art active matrix organic electroluminescence display device and a method of manufacturing the same will be described with reference to the accompanying drawings.
FIG. 2
is a layout of the related art active matrix organic electroluminescence display device of FIG.
1
.
FIG. 3
is a sectional view of the related art active matrix organic electroluminescence display device taken along line I-I′ of FIG.
2
.
First and second semiconductor layers
4
a
and
5
a
having an island-shape are formed on portions of a substrate
10
where the switching and driving transistors
4
and
5
will be formed, respectively. At this time, an amorphous silicon a-Si:H is deposited on entire surface of the substrate. Then, the amorphous silicon is crystallized to a polysilicon in a scanning method using an excimer laser and is selectively removed to form the first and second semiconductor layers
4
a
and
5
a.
A gate insulating layer
30
is formed on the entire surface of the substrate
10
including the first and second semiconductor layers
4
a
and
5
a
. Then, the scan line
1
is formed to cross the first semiconductor layer
4
a
on the gate insulating layer
30
, and the gate electrode of the driving transistor
5
b
is formed to cross the second semiconductor layer
5
a
. At this time, the scan line
1
and the gate electrode
5
b
of the driving transistor are isolated from each other, and the gate electrode
5
b
is widened at a certain portion to form a capacitor overlapped with the power line
3
, which will be formed in a later step.
Impurity ions are injected to the first and second semiconductor layers at both sides of the scan line
1
and the gate electrode
5
b
of the driving transistor, thereby forming source/drain regions, respectively.
Accordingly, the switching transistor
4
is formed by the scan line
1
and the first semiconductor layer
4
a
, and the driving transistor
5
is formed by the gate electrode
5
b
and the second semiconductor layer
5
a.
An insulating interlayer
50
is formed on the entire surface of the substrate including the scan line
1
and the gate electrode
5
b
, and then contact holes are respectively formed at source and drain regions and the gate electrode
5
b
of the first semiconductor layer
4
a
, and the source region of the second semiconductor layer
5
a.
The data line
2
connected with the source region of the first semiconductor layer
4
a
is formed perpendicular to the scan line
1
on the insulating interlayer
50
. The power line
3
connected with the source region of the second semiconductor layer
5
a
is formed perpendicular to the scan line
1
to be overlapped with the gate electrode
5
b
. Then, an electrode pattern
20
is formed to connect the drain region of the first semiconductor layer
4
a
to the gate electrode
5
b
. At this time, the capacitor
6
is formed in a portion where the gate electrode
5
b
and the power line
3
overlap each other.
Then, an insulating layer
70
for planarization is formed on the entire surface of the substrate
10
. The contact hole is formed at the drain region of the second semiconductor layer
5
a
on the insulating layer
70
, thereby forming the electroluminescence device
7
connected to the drain region.
A method of manufacturing the related art active matrix organic electroluminescence display device having the above structure will be described as follows.
The amorphous silicon a-Si:H is deposited on the substrate
10
, and then is crystallized to the polysilicon by an exicmer laser. Then, the crystallized polysilicon is selectively removed to form the first and second semiconductor layers
4
a
and
5
a
having an island shape corresponding to portions where the switching and driving transistors
4
and
5
will be formed, respectively.
A method for crystallizing the amorphous silicon to the polysilicon by the scanning method of the excimer laser will be described in detail.
FIG. 4
is a plan view for illustrating the method of crystallizing according to a related art laser annealing method (scanning method).
A laser beam having a width of 0.5 mm or less and a length shorter than an LCD panel is emitted to the amorphous silicon for crystallizing the amorphous silicon as polysilicon in the scanning method. At this time, the laser beam is transferred at 25 &mgr;m per pulse from one side of the LCD panel to other side vertically.
The gate insulating layer
30
is formed on the entire surface of the substrate
10
including the first and second semiconductor layers
4
a
and
5
a
, and then a metal layer is deposited on the entire surface of the substrate. Then, the metal layer is selectively removed to form the scan line
1
crossing the first semiconductor layer
4
a
on the gate insulating layer
30
, simultaneously, to form the gate electrode
5
b
of the driving transistor crossing the second semiconductor layer
5
a
. At this time, the scan line
1
and the gate electrode
5
b
of the driving transistor are isolated from each other. Then the gate electrode
5
b
is widened at a certain portion to form a capacitor overlapped with the power line
3
, which will be formed in a later step.
Impurity ions are injected to the first and second semiconductor layers
4
a
and
5
a
using the scan line
1
and the gate electrode
5
b
of the driving transistor as masks, thereby form
Kim Sung Ki
Park Jae Yong
Alemu Ephrem
LG.Philips LCD Co. , Ltd.
McKenna Long & Aldridge LLP
Wong Don
LandOfFree
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