Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-06-24
2004-12-14
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185190, C365S185220
Reexamination Certificate
active
06831864
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a nonvolatile semiconductor memory unit in which data can be written and erased electrically and more particularly, to a method of erasing data of a nonvolatile semiconductor memory (hereinafter, referred to as a “flash memory”), in which the data is erased in all memory cells collectively or in units of memory blocks each having a set of the memory cells.
2. Description of the Prior Art
The flash memory uses, as memory cells, transistors (hereinafter, referred to as “memory transistors”) each of which has a floating gate and variable threshold voltage. As disclosed in, for example, Japanese Patent Laid-Open Publication No. 2001-283595 (2001), a conventional flash memory includes a memory cell array which, in turn, includes a plurality of nonvolatile memory transistors arranged in rows and columns, a plurality of word lines for selecting the rows of the memory transistors, respectively and a plurality of bit lines corresponding to the columns of the memory transistors, respectively and is divided into a plurality of memory blocks each having a set of the memory transistors. The conventional flash memory further includes a potential generating portion for generating a potential applied to the word lines, the bit lines and substrates and sources of the memory transistors and a write/erase control portion for controlling the potential generating portion so as to erase data in all the memory transistors collectively or in units of the memory blocks.
A data erase method of the conventional flash memory of the above described configuration is disclosed in, for example, FIG. 42 of the prior art document referred to above. This known data erase method includes a first step of collectively applying a preliminary write pulse to the memory transistors, a second step of collectively applying a first erase pulse to the memory transistors and repeating, if it is judged that erase has not been completed, the first erase pulse application operation with change of intensity of the first erase pulse until it is judged that erase has been completed, a third step of collectively applying a write pulse to the memory transistors and repeating, if it is judged that recovery has not been completed, the write pulse application operation with change of intensity of the write pulse until it is judged that recovery has been completed, a fourth step of collectively applying a second erase pulse to the memory transistors and repeating, if it is judged that erase has not been completed, the second erase pulse application operation with change of intensity of the second erase pulse until it is judged that erase has been completed, and a fifth step of repeating, if the memory transistors are in an overerased state, a selective recovery operation on the memory transistors until the memory transistors are not in the overerased state.
In the above known data erase method, the first erase pulse application operation is performed prior to the first erase verify operation in the second step, the write pulse application operation is performed prior to the recovery verify operation in the third step and the second erase pulse application operation is performed prior to the second erase verify operation in the fourth step.
Therefore, in the above known data erase method, since the pulse application operation is inevitably performed prior to the verify operation in the second to fourth steps even if the pulse application operation is not necessary actually, it is difficult to stabilize and speed up the erase operation.
SUMMARY OF THE INVENTION
Accordingly, an essential object of the present invention is to provide, with a view to eliminating the above mentioned drawbacks of prior art, a method of erasing data of a nonvolatile semiconductor memory unit, in which by performing a verify operation prior to a pulse application operation, an unnecessary pulse application operation is eliminated such that it is possible to stabilize and speed up an erase operation.
In order to accomplish this object of the present invention, a data erase method of the present invention is applied to a nonvolatile semiconductor memory unit including a memory cell array which is provided with a plurality of nonvolatile memory transistors arranged in rows and columns, a plurality of word lines for selecting the rows of the memory transistors, respectively and a plurality of bit lines corresponding to the columns of the memory transistors, respectively and is divided into a plurality of memory blocks each having a set of the memory transistors, a potential generating portion for generating a potential applied to the word lines, the bit lines and substrates and sources of the memory transistors and a write/erase control portion for controlling the potential generating portion so as to erase the data in the memory transistors collectively or in units of the memory blocks.
The data erase method includes the first step of collectively applying a preliminary write pulse to the memory transistors, the second step of repeating, if the memory transistors are not in a first erased state, an operation of collective application of a first erase pulse to the memory transistors with change of intensity of the first erase pulse in second and subsequent application operations of the first erase pulse until the memory transistors assume the first erased state, the third step of repeating, if the memory transistors are not in a recovered state, an operation of collective application of a write pulse to the memory transistors with change of intensity of the write pulse in second and subsequent application operations of the write pulse until the memory transistors assume the recovered state, the fourth step of repeating, if the memory transistors are not in a second erased state, an operation of collective application of a second erase pulse to the memory transistors with change of intensity of the second erase pulse in second and subsequent application operations of the second erase pulse until the memory transistors assume the second erased state and the fifth step of repeating, if the memory transistors are in an overerased state, a selective recovery operation on the memory transistors until the memory transistors are not in the overerased state.
REFERENCES:
patent: 6243292 (2001-06-01), Kobayashi et al.
patent: 6330192 (2001-12-01), Ohba et al.
patent: 6388921 (2002-05-01), Yamamoto et al.
patent: 6515908 (2003-02-01), Miyawaki et al.
patent: 2001-283595 (2001-10-01), None
Futatsuya Tomoshi
Hayasaka Takashi
Mizoguchi Shinichi
Dinh Son T.
McDermott Will & Emery LLP
Renesas Technology Corp.
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