Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1995-10-02
2001-01-23
Saras, Steven J. (Department: 2775)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S204000
Reexamination Certificate
active
06177920
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a driver circuit for a display device, and in particular, to a driver circuit suitable use in a liquid crystal display device.
Recently, a line sequential scanning circuit using a shift register has been mainly used as a driver circuit for a display device such as a liquid crystal display device of an active matrix type.
Gradation signals for providing a gradation display are classified into the digital system and the analog system. In both systems, a signal is input to registers which are connected in series by n-stages (n: the number of pixels in a horizontal direction or vertical direction) so as to be delayed and transmitted, thereby performing a line sequential scanning operation.
Each register is connected with a sample and hold circuit and a signal amplifying circuit, and a signal which has passed through those circuits is transmitted to a pixel portion through a signal line.
A schematic diagram of the overall liquid crystal display device is shown in FIG.
1
.
A signal line driver circuit
101
and a scanning line driver circuit
102
are arranged on the same glass substrate, and a liquid crystal pixel portion
103
is disposed in the center portion of the display device.
The signal line driver circuit
101
and the liquidcrystal pixel portion
103
are connected to each other through vertical signal lines X
1
, X
2
, . . . , whereas the scanning line driver circuit
102
and the liquid crystal pixel portion
103
are connected to each other through horizontal scanning lines Y
1
, Y
2
, . . . Thin film transistors (TFTs) as switching elements are disposed on the respective intersections of the signal lines and the scanning lines in the form of a matrix.
A source electrode of the TFT is connected to the signal line, a gate electrode thereof is connected to the scanning line thereof, and a drain electrode thereof is connected to a pixel electrode of the liquid crystal pixel portion
103
. The pixel electrode is opposed to a counter electrode through the liquid crystal.
Signals are transmitted from the scanning line driver circuit
102
to the liquid crystal pixel portion
103
through the scanning lines Y
1
, Y
2
, . . . in synchronism with a timing at which the signal lines X
1
, X
2
, . . . are sequentially driven by the signal line driver circuit
101
, thereby providing a signal necessary for image display.
An example of the line sequential driver circuit of the analog system type is shown in FIG.
2
. In
FIG. 2
, numeral
220
is a signal line driver circuit, and numeral
201
is a scanning line driver circuit.
In the signal line driver circuit
201
, a shift register
200
is connected with a source voltage Vdd
202
, Vss
203
and a clock pulse CP
204
, and an input start pulse SP
205
is delayed by and transmitted through flip-flop circuits (F.F. circuits) connected in series inside thereof.
The outputs of the shift registers
200
constructed by n-stage serial connections are Q
0
, Q
1
, . . . Qn. Using those outputs as a timing signal, a video signal
206
is output to a sampling circuit (not shown) through an analog switch
207
. In the sampling circuit, gradation data is sampled. Sampled analog gradation data is stored in an analog memory
208
, which constitutes a sample and hold circuit, once before the data is input to a pixel portion.
In accordance with a scanning timing due to a latch pulse
209
input from the external, the analog gradation data stored in the analog memory
208
is subjected to an impedance conversion by an analog buffer
210
before the data is transmitted to a pixel portion
212
through a signal line
211
.
The above path is obtained through the shift register
200
at each stage so that the image line sequential scanning operation is conducted.
In this example, the line sequential scanning driver circuit of the analog system is described. In the digital system, the analog memory
208
is replaced by a latch circuit for storing the gradation data.
However, in any of the analog or digital systems, since the line sequential scanning operation is conducted using a shift register, if there exists even one defective circuit in the shift register connected by a plurality of stages, a signal is not transmitted to the registers which are arranged at-the stages subsequent to the stage where the defective circuit exists. As a result, an excellent display state cannot be obtained, and yield for the display device is lowered.
In a general projection type display device, represented by a liquid crystal projector shown in
FIG. 4
, three liquid crystal light valves
401
,
402
and
403
for R (red), G (green) and B (blue) are independently used in the three plate type. A light irradiated from a lamp is polarized by a polarizing prism and separated into red polarization, green polarization and blue polarization by a dichroic mirror. While the light is separated, a red polarization component, a green polarization component, and a blue polarization component are incident to a red liquid crystal panel, a green liquid crystal panel, and a blue liquid crystal panel, through a projection lens, respectively.
In this situation, after passing through the light valves
401
,
402
and
403
, the green polarization component and the blue polarization component are reversed an even number of times by a reflecting mirror while the red polarization component is reversed an odd number of times. Consequently, since a red image must be finally reversed, a selection direction of the scanning lines (or signal lines) for red images in a driver circuit must be reversed to that for green and blue images.
In the general driver circuit, one scanning line driver circuit is disposed on the display device side. For example, in
FIG. 5A
, in order to conduct the backward selection of the scanning lines, a scanning line driver circuit for a forward selection may be disposed on one side of the liquid crystal pixel portion, whereas a scanning line driver circuit for a backward selection may be disposed on an opposite side thereof. Alternatively, in
FIG. 5B
, a scanning line driver circuit for the forward selection as well as a scanning line driver circuit for the backward selection is disposed on one side of the liquid crystal pixel portion. With those arrangements, a bi-directional driver circuit is constructed.
Compared with the manufacture of two kinds of display devices for the forward and backward selections, the above arrangement does not require two kinds of masks for manufacturing, and does not increase the manufacturing steps, thereby being capable of lowering the costs. However, since the number of drive circuits are increased, the display device per se cannot be prevented from becoming large in size. Also, the frequency of the defects is increased, which a significant factor that causes the yield to be lowered.
In the conventional line sequential scanning of the delay signal transmission system using the shift register, one defective circuit causes a signal not to be transmitted to the succeeding circuit thereby making the entire circuit inoperable. As a result, an excellent display cannot be obtained, and a yield is lowered in the entire display device. Also, to obtain the reverse image, two kinds of driver circuits, having a driver circuit for the forward selection and a driver circuit for the backward selection, are required.
SUMMARY OF THE INVENTION
To improve the foregoing drawback, the inventors of the present invention conceived a decoder driver circuit which directly selects a display pixel portion in accordance with an address signal by replacing the shift register portion by a decoder circuit.
FIG. 3
is a circuit block diagram showing a decoder driver circuit of the digital system.
An address signal of a pixel to be displayed is input to an address decoder
301
from an external terminal, and a display pixel is selected as a binary digital signal in the address decoder
301
.
The address signal constitutes a latch pulse
303
input to first latch circuits
302
connected in parallel to each
Koyama Jun
Suzuki Ritsuko
Bell Paul A.
Cook Alex McFarron Manzo Cummings & Mehler, Ltd.
Saras Steven J.
Semiconductor Energy Laboratory Co,. Ltd.
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