Low-noise amplifier stage with matching network

Details Low-noise amplifier stage with matching network Low-noise amplifier stage with matching network

1999-12-21

2001-08-21

Shingleton, Michael B (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including frequency-responsive means in the signal...

C330S306000, C330S311000

Reexamination Certificate

active

06278329

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a low-noise RF (radio frequency) amplifier stage with matching network.
BACKGROUND OF THE INVENTION
As known, a high-performance unit in modern transceivers is formed by an RF (radio frequency) LNA (Low Noise Amplifier), located in the receiver chain, immediately after the antenna, or in cascade to the RF band-pass filter, connected to the antenna.
In a low-noise amplifier for the above application, the most critical parameters are noise figure F (defined as 10Log(SNR
in
/SNR
out
), wherein SNR
in
and SNR
out
are, respectively, the input and output signal to noise ratio), and linearity. In fact, the amplifier operates on high dynamic signals having minimum levels, in many cases lower than −100 dBm. Other important parameters of an LNA are gain and input matching, whereas output matching is usually less critical, or is not required at all, since, in a monolithic transceiver, the low-noise amplifier is disposed a few tens of &mgr;um away from the mixer, connected to the LNA output.
Matching at the input requires particular care, not only to obtain a low VSWR (Voltage Standing Wave Ratio), but above all because, as is well known, the noise figure F is strongly dependent on the matching network, arranged between the source (antenna) and the LNA itself. Therefore, the present trend is to design the matching,u network simultaneously with the low-noise amplifier, such as to obtain optimum design of the entire amplifier stage.
The more commonly used low-noise amplifier configuration with matching network is shown in FIG.
1
and is described hereinafter. The low-noise amplifier stage
1
comprises a first and a second transistor
2
,
3
of NPN type, connected between a first supply line
4
set to V
cc,
and a second supply line
5
set to V
EE
. In detail, the first transistor
2
has a base terminal
10
connected to an input terminal
11
through a first inductor
12
; an emitter terminal
15
connected to the second supply line
5
through a second inductor
16
; and a collector terminal
17
connected to the emitter terminal of the second bipolar transistor
3
. The latter has a base terminal
20
biased to a constant voltage V
B
, and a collector terminal (forming an output terminal
21
of the amplifier stage
1
) connected to the first supply line
4
through a load resistor
22
.
An input voltage V
i
is supplied to the input terminal
11
, and an output voltage V
o
is present at the output terminal
21
.
In the circuit of
FIG. 1
, the inductors
16
and
12
form the matching network, and are used to guarantee matching, respectively of the real part and of the imaginary part of the input impedance (impedance of the amplifier stage
1
, seen from input terminal
11
).
The circuit in
FIG. 1
has a small signal model shown in FIG.
2
. wherein the various noise sources are represented by voltage or current sources.
In detail,
FIG. 2
shows a generator noise voltage source
25
, representing the noise associated with the signal generator (the antenna, in this specific application), and the respective resistance R
S
(resistor of the source
26
), in series with the first inductor
12
; in turn, the latter (which has inductance L
B
) is connected in series with a base resistor
27
, representing the base resistance of the first transistor
2
, and with a pair of voltage sources
28
and
29
, representing the thermal noise S
Vb
and S
Ve
associated respectively with the base resistance and with the emitter resistance (brought back to the input) of the first transistor
2
.
The terminal of the emitter noise voltage source
29
not connected to the base noise voltage source
28
forms a node
30
; between the node
30
and the node
31
are arranged, in parallel with one another, a base noise current source
32
, representing the shot noise S
lb
associated with the base region of the first transistor
2
; a first capacitor
33
, representing the capacitance C
&pgr;
between the base region and the emitter region; and an input resistor
34
, representing the input small signal resistance r
&pgr;
. A second capacitor
35
, representing the base-collector capacitance C
&mgr;
, is connected between node
30
and collector terminal
17
; between the collector terminal
17
and a node
31
, are connected, in parallel with one another, a gain current source
36
, substantially representing the collector current of the first transistor
2
, equivalent to g
m
V
be
, wherein g
m
is the transconductance of the first transistor
2
, and V
be
is the voltage drop between nodes
30
and
31
. and a first collector noise current source
37
, representing the shot noise S
lc
associated with the collector region of first transistor
2
.
Collector terminal
17
is connected to output node
21
through a uniform gain current buffer
40
, representing the second transistor
3
; in addition, a load noise current source
41
is connected between node
21
and ground line and represents thermal noise S
IRc
associated with load resistor
22
.
In
FIG. 2
, an emitter resistor
38
is connected between node
31
and emitter terminal
15
, and represents the resistance r
e
of the emitter region.
Using the model in
FIG. 2
, on the assumption that:
(
ω
·
β
ω
T
)
⪢
1
wherein &bgr; is the current gain of first transistor
2
, and &ohgr;
T
is the cut-off frequency of the transistor, defined as g
m
/(C
&mgr;
+C
&pgr;
). The conductance Y
&pgr;
provided by the parallel connection of first capacitor
33
and input resistor
34
is provided by:
Y
π
=
j
⁢
 
⁢
ω
⁢
 
·
C
π
+
1
r
π
≈
j
⁢
 
⁢
ω
·
C
π
(
1
)
and, since resistance r
e
is not known (resistor
38
), input impedance Z
in
(impedance of the amplifier stage
1
seen from the input terminal
11
), is provided by:
Z
in
⁡
(
j
⁢
 
⁢
ω
)
≅
ω
T
·
L
E
+
r
b
-
j
⁢
 
⁢
1
ω
·
(
C
π
+
C
μ
)
+
j
⁢
 
⁢
ω
·
(
L
B
+
L
E
)
(
2
)
In the circuit in
FIG. 1
, the matching condition for the input impedance Z
in
(j&ohgr;)=R
s
requires selection of values for L
B
and L
E
which satisfy the following equations:
&ohgr;
T
·L
E
+r
b
≅R
S
  (3)
&ohgr;
2
·(
L
B
+L
E
)·(
C
&pgr;
+C
&mgr;
)≅1  (4)
In the model of
FIG. 2
, the second transistor
3
has been considered as an ideal current buffer, free from noise. In this hypothesis, and in the conditions of matching according to (3) and (4), the noise factor NF, equivalent to SNR
in
/SNR
out
, is provided by:
NF
≈
1
+
r
b
+
r
e
R
S
+
1
2
·
g
m
·
R
S
·
(
1
+
r
b
R
S
)
2
·
[
1
β
+
(
ω
ω
T
)
2
]
+
1
2
·
β
·
g
m
·
R
S
·
(
ω
T
ω
)
2
+
R
S
R
C
·
(
ω
ω
T
)
2
(
5
)
wherein the inductors
12
,
16
have been considered ideal. The contribution of the real inductors can be calculated by connecting resistors in series to the base resistor
27
and emitter resistor
38
.
SUMMARY OF THE INVENTION
A low-noise amplifier stage with a matching network with improved noise figure is provided.
The disclosed embodiments of the invention are directed to an amplifier stage having a first and a second transistor element connected in series to each other between a first and a second reference potential line, the first transistor having a control terminal connected to an input of the amplifier stage through a first inductive elements a first terminal connected to the second reference potential line through a second inductive element, and a third terminal connected to a first terminal of the second transistor element; the second transistor element having a second terminal forming an output of the amplifier stage and connected to the first reference potential line through a lode element; and a capacitive element connected between the control terminal and the fi

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