Active load for an N channel logic network

Details Active load for an N channel logic network Active load for an N channel logic network

1997-03-19

1999-07-20

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 17, 326 45, H03K 19096, H03K 19017

Patent

active

059260394

ABSTRACT:
An active load (12) is provided for an N channel logic network (10). The active load (12) includes a P channel device (28) coupled to the output node (14) of the N channel network (10). A clock circuit (16) of the active load (12) determines whether the N channel network (10) is in a steady state or a switching mode. If the N channel network (10) is in a switching mode, an intermediate voltage level, V.sub.bias, is applied at the gate of the P channel device (28) to facilitate fast switching at the output node (14) with low quiescent power consumption and without compromising compact semiconductor layout.

REFERENCES:
patent: 4782249 (1988-11-01), Engeler et al.
patent: 5121005 (1992-06-01), Parker
patent: 5619153 (1997-04-01), Shenoy et al.
patent: 5670898 (1997-09-01), Fang

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