Active float for the dummy bit lines in FeRAM

Details Active float for the dummy bit lines in FeRAM Active float for the dummy bit lines in FeRAM

2005-09-15

2008-12-09

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000, C365S189090

Reexamination Certificate

active

07463504

ABSTRACT:
Methods are described for operating a FeRAM and other such memory devices in a manner that avoids over-voltage breakdown of the gate oxide in memory cells along dummy bit lines used at the edges of memory arrays, the methods comprising floating the dummy bit line during plate line pulsing activity. In one implementation of the present invention the method is applied to a FeRAM dummy cell having a plate line, a dummy bit line, a pass transistor, and a ferroelectric storage capacitor. The method comprises initially grounding the dummy bit line as a preferred pre-condition, however, this step may be considered an optional step if the storage node of the storage capacitor is otherwise grounded. The method then comprises floating the dummy bit line, activating a word line associated with the memory cell, and pulsing the plate line. Alternately, the method comprises applying a positive voltage bias to the dummy bit line in place of, or before floating the dummy bit line. The method may further optionally comprise grounding the dummy bit line after pulsing the plate line, and optionally disabling the word line after grounding the dummy bit line to precondition the cell for the next memory operation.

REFERENCES:
patent: 6046928 (2000-04-01), Takata
patent: 6356475 (2002-03-01), Tamura et al.
patent: 6407943 (2002-06-01), Choi et al.
patent: 6898145 (2005-05-01), Winograd et al.
patent: 6990005 (2006-01-01), Saito
patent: 2006/0013033 (2006-01-01), Yamamura

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