Active failsafe detection for differential receiver circuits

Details Active failsafe detection for differential receiver circuits Active failsafe detection for differential receiver circuits

2005-07-05

2005-07-05

Beausoliel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S047300, C714S056000, C714S721000

Reexamination Certificate

active

06915459

ABSTRACT:
The present invention provides a method, system and apparatus for providing failsafe detection for a differential receiver. A bus activity signal (11) is activated when receiving a differential data signal of sufficient amplitude to transition through a predetermined threshold. A failsafe signal (620) indicates a low differential voltage condition. A countdown time period commences (85) upon activation of either signal, and a failsafe condition is determined (89) to exist if the failsafe signal is active (87) when the countdown time period expires (86).

REFERENCES:
patent: 5488306 (1996-01-01), Bonaccio
patent: 5867775 (1999-02-01), Shirai et al.
patent: 6111437 (2000-08-01), Patel
patent: 6147515 (2000-11-01), Ang et al.
patent: 6493401 (2002-12-01), Erckert

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