Active circuit for synthesizing an inductor

Details Active circuit for synthesizing an inductor Active circuit for synthesizing an inductor

2002-04-02

2004-03-16

Lee, Benny (Department: 2817)

Wave transmission lines and networks

Negative resistance or reactance networks of the active type

Simulating specific type of reactance

C333S216000

Reexamination Certificate

active

06707354

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to active circuits, in particular active inductors, which are incorporated in integrated circuits.
STATE OF THE ART
Active inductors have been described, for example in document U.S. Pat. No. 6,028,496, which is related to a device comprising two Operational Amplifiers (OPAMPS). The active inductor of this document includes an inverting amplifier of a common source (common emitter) type, which inversely amplifies an input signal and outputs the amplified signal as an output signal, a non-inverting amplifier of a common gate (common base) type, which non-inversely amplifies the output signal and the amplified signal as the input signal, a capacitor connected between the input signal and a reference signal, and a biasing portion for biasing the inverting amplifier and the non-inverting amplifier.
A general drawback of these existing active inductors is the fact that they all comprise at least two Operational Amplifiers, leading to a relatively high power consumption.
AIMS OF THE INVENTION
The present invention aims to provide an active inductor which consumes less power compared to the active inductors belonging to the current state of the art.
SUMMARY OF THE INVENTION
The present invention is related to an apparatus comprising an active circuit, the circuit synthesising an inductor, characterised in that the circuit comprises one Operational Amplifier.
According to a preferred embodiment, the invention is related to an apparatus comprising an active circuit, wherein the circuit comprises:
an Operational Amplifier with a non-inverting input terminal, an inverting input terminal, a non-inverting output terminal and an inverting output terminal,
a first resistor R
1
and a first capacitance C
1
, connected in cascade between the inverting input terminal and a first output terminal of the active circuit,
a second resistor R
1
′, having the same resistance as R
1
, and a second capacitance C
1
′, having the same capacitance value as C
1
, connected in cascade between the non-inverting input terminal and a second output terminal of said the active circuit,
a third resistor R
2
and a fourth resistor R
3
, connected in cascade between the non-inverting input terminal and the first output terminal of the circuit,
a fifth resistor R
2
′, having the same resistance as R
2
, and a sixth resistor R
3
′, having the same resistance as R
3
, the resistors R
2
′ and R
3
′ being connected in cascade between the inverting input terminal and the second output terminal of the circuit,
a seventh resistor Rx and a third capacitance Cx, connected in parallel, and coupled between the inverting output terminal and a common node of the third resistor R
2
and the fourth resistor R
3
,
an eighth resistor Rx′, having the same resistance as Rx, and a fourth capacitance Cx′, having the same capacitance value as Cx, the resistor Rx′ and the capacitance Cx′ being connected in parallel, and coupled between the non-inverting output terminal and a common node of the fifth resistor R
2
′ and the sixth resistor R
3
′,
a ninth resistor R
4
connected between the inverting output terminal and the first output terminal of the circuit, and an tenth resistor R
4
′, connected between the non-inverting output terminal and the second output terminal of said circuit.
According to the preferred embodiment of the present invention, the resistance values of R
4
and R
4
′ obey the following formula:
R4
=
R4
′
=
(
C1
·
R1
+
(
2
⁢
C1
-
Cx
)
·
Rx
)
·
R3
+
C1
·
R1
·
Rx
Cx
·
Rx
-
C1
·
R1
According to a further embodiment, the invention is related to an apparatus wherein the inductor synthesised by said active circuit is tuneable. This may be realised by making the capacitors C
1
, C
1
′, Cx and Cx′ tuneable.
According to another embodiment, the ratio between C
1
and Cx is constant.
According to another embodiment, the value Rx.Cx is greater than R
1
.C
1
.


REFERENCES:
patent: 3993968 (1976-11-01), Lee
patent: 4513265 (1985-04-01), Sokoloff
patent: 6028496 (2000-02-01), Ko et al.
patent: 3009118 (1981-09-01), None
patent: 53065041 (1978-06-01), None
patent: 101111 (1987-05-01), None
patent: 1073885 (1984-02-01), None
A. W. Keen et al, “Inductance simulation with a Single Differential-Input Operational Amplifier”, Electronics Letters, vol. 3, No. 4, Apr. 1, 1967 , pp. 136-137 XP002175043.

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