Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-05-11
2004-03-30
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S249000, C257S395000, C257S500000, C257S647000
Reexamination Certificate
active
06713822
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
The entire disclosure of Japanese Patent Application No. Hei 10-14352 filed on Jan. 27, 1998 including specification, claims, drawings and summary are incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a technique for improving the component separating function of a semiconductor device.
2. Description of the Related Art
MOS type field effect transistors (Metal Oxide Semiconductor Field Effect Transistor) are known as semiconductor components.
FIG. 8
is a conceptual figure of a flat structure of a semiconductor device comprising conventional MOS type field effect transistors (referred to at times hereafter simply as “transistor”).
FIG. 9
shows cross-section
9
—
9
of FIG.
8
.
As shown in
FIG. 9
, a transistor
12
is formed within this semiconductor device. The transistor
12
comprises a channel forming region CH which is sandwiched between source S
1
and drain D
1
(see FIG.
8
).
A gate electrode
22
is formed on the channel forming region CH via a gate oxide film
20
. An interlayer film
24
is formed on the gate electrode
22
. An aluminum wiring
28
is formed on the interlayer film
24
. The gate electrode
22
and the aluminum wiring
28
are connected via a contact hole
26
which is formed in the interlayer film
24
.
Another transistor
14
is formed on the semiconductor device separately from the transistor
12
via a field oxide film
18
for component separation. Thus, by interposing the field oxide film
18
between the two transistors
12
and
14
, it is possible to separate the transistors electrically.
However, such conventional semiconductor devices have the following type of problems. As shown in
FIG. 9
, the contact hole
26
for connecting the gate electrode
22
and the aluminum wiring
28
is formed on the field oxide film
18
. Therefore, part of the gate electrode
22
of the transistor
12
is placed directly on top of the field oxide film
18
.
Thus, when a voltage is applied to the gate electrode
22
, there is a possibility of the surface of semiconductor layer
16
(the part shown by the “x” mark in the figure) directly below the field oxide film
18
being inverted. There is a particularly high risk for this with high withstand voltage transistors for which a high voltage is applied to the gate electrode
22
. If the surface of the semiconductor layer
16
beneath the field oxide film
18
is inverted, the inverted portion will not function as a component separating region.
To electrically separate the transistor
12
and the transistor
14
to avoid this situation, a sufficiently large length L
1
of the non-inverted part can be secured. However, with this method, the overall length L
2
of the field oxide film
18
becomes long, so the layout space for the transistor
12
and the transistor
14
becomes large. This leads to a reduction in the degree of integration of the semiconductor device.
Another method that can be considered to avoid the problem described above is making the film thickness of the field oxide film
18
thick. However, if the overall length L
2
of the field oxide film
18
is left as is and the film thickness is increased, the incline angle of the area near the edge (bird's beak area)
18
a
of the field oxide film
18
becomes large, and the degree of concentration of the electrical field for the edge area
18
a
becomes larger. This makes it impossible to obtain the desired withstand voltage.
Also, if the film thickness of the field oxide film
18
is increased, a greater time is required for forming the field oxide film
18
, so production efficiency is lowered, and production costs are increased.
As a further method for avoiding the problems described above, we can consider a method of increasing the density of channel stop ions implanted into the surface of the semiconductor layer
16
which is under the field oxide film
18
. However, if the density of the channel stop ions is increased, there is a decrease in the withstand voltage.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device that solves these types of problems and that can separate components easily.
In accordance with characteristics of the present invention, there is provided a semiconductor device comprising:
a base semiconductor layer,
an insulation film for separating components formed on the base semiconductor layer, and
a semiconductor component which is formed on the base semiconductor layer in a component forming region separated by the insulation film for separating components, the semiconductor component having a first conductive layer,
wherein the semiconductor device comprises:
an interlayer insulation film placed on the insulation film for separating components and the first conductive layer, and
a second conductive layer placed on the interlayer insulation film,
wherein the first conductive layer is substantially formed only within the component forming region, and
wherein the first conductive layer and the second conductive layer are substantially connected only within the component forming region.
In accordance with characteristics of the present invention, there is provided a wiring method for a semiconductor device comprising an insulation film for separating components formed on a base semiconductor layer, wherein wiring is substantially performed using a first wiring layer only within a component forming region separated by the insulation film for separating components;
wiring is performed using a second wiring layer on an interlayer insulation film formed on the insulation film for separating components and the first wiring layer;
the first wiring layer and the second wiring layer are substantially connected only within the component forming region.
The characteristics of the present invention are broadly indicated as noted above, but the structure, contents, object, and features will be clearer through reference to the figures and according to the following disclosure.
REFERENCES:
patent: 4543592 (1985-09-01), Itsumi et al.
patent: 5200637 (1993-04-01), Matsuo et al.
patent: 5610101 (1997-03-01), Koyama
patent: 5811862 (1998-09-01), Okugaki et al.
patent: 6097066 (2000-08-01), Lee et al.
patent: 07-74353 (1995-05-01), None
patent: 9-307091 (1997-11-01), None
Merchant & Gould P.C.
Rohm & Co., Ltd.
Warren Matthew E.
Wilson Allan R.
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