Active bit line charge keeper

Details Active bit line charge keeper Active bit line charge keeper

2007-08-14

2009-12-01

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S189140, C365S189150, C365S189160, C365S189190, C365S204000

Reexamination Certificate

active

07626878

ABSTRACT:
One embodiment of the present invention sets forth an active bit line charge keeper circuit for improving the reliability of a static random access memory (SRAM) circuit. The active bit line charge keeper circuit includes two sub-circuits, each disposed between bit line pairs within the SRAM circuit. The first sub-circuit mitigates residual state associated with over-developed read state on the bit lines. The second sub-circuit mitigates the effects of residual state associated with reading one value on a given pair of bit lines and subsequently writing a different value. By mitigating the effects of residual state within an SRAM circuit, higher reliability at a given performance level may be achieved.

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Office Action. U.S. Appl. No. 11/838,785 dated Jun. 18, 2009.

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