Active accelerated discharge of a capacitive system

Details Active accelerated discharge of a capacitive system Active accelerated discharge of a capacitive system

1998-10-02

2001-01-30

Ray, Gopal C. (Department: 2781)

Electrical computers and digital processing systems: support

Computer power control

C713S340000

Reexamination Certificate

active

06182230

ABSTRACT:

BACKGROUND
1. Field of the Present Invention
The present invention generally relates to capacitive discharge in an electronic system and more specifically to a circuit for rapidly eliminating charged stored in a computer system during a temporary loss of system power.
2. History of Related Art
Microprocessor based computing systems are widely used for personal, business, scientific, and government applications. The price-to-performance ratio of these machines has improved so dramatically in the 1990's that microprocessor based computers are now used for tasks previously reserved for workstations and mainframe computers such as performance demanding applications and large network controllers. The increased expectations placed on these machines by consumers have forced manufacturers of personal computers and other similar microprocessor based machines to devote increased attention to reliability issues. Consumers who rely on microprocessor based machines to run entire networks, maintain financial information including payroll, accounts receivable, accounts payable, and other critical functions require essentially zero down time.
Many modem computer systems include power management modules designed to minimize and monitor the power consumed by the computer system. Power management modules may include functionality designed to place system components in low power or standby mode if a particular device experiences no activity for a specified duration. While these modules are highly desirable to reduce the tremendous power consumed by high performance computer systems, the power management system adds complexity to the computer system. In addition to power management modules, typical computer systems include a variety of subsystems in addition to the core circuitry comprised of the microprocessor and its support devices. Each of these core systems and sub-systems includes thousand of logic gates interconnected by a network of interconnect structures. Reliable operation requires that each of the systems and their component pieces be initiated or powered up in a known state. Once a known state has been achieved, the computer system inputs and outputs may then be manipulated and monitored to transition the computer system from one known state to a next known state in a predictable manner. The predictability of the computer system is an essential feature of any state machine and is obviously a cornerstone of reliable operation.
Predictability can be lost, however, if the computer system is operated before achieving a known or initial state. Computer systems may be inadvertently and undesirably forced into an unknown or indeterminate state by a variety of mechanisms. One not too uncommon scenario that can wreak havoc with the various modules of a computer system occurs when the power supply voltage is briefly or temporarily disrupted. Line disturbances and other relatively brief interruptions in the steady supply of power to a computer system can force the system into an unknown state by initiating a power up sequence before the system has achieved a suitable power off condition. Due to the sometimes large system or bulk capacitance associated with computer systems, energy or charge stored in the system may require a relatively long time to fully achieve a zero power or “off” state. If a comparatively brief line disturbance occurs, it is entirely possible that a power up sequence is initiated before the computer has reached a steady state condition. Under these circumstances, the computer system may be in any of an essentially infinite number of states when the power up sequence is initiated. The state of the computer system that results when a power up sequence is initiated under such circumstances can be unpredictable. This unpredictability presents a serious reliability concern to users and makers of computer systems, especially in view of the inevitability of power outages and external line disturbances, which are almost universally beyond the control of the computer user and manufacturer alike. Accordingly, it would be highly desirable to provide a practical solution to assist computer systems in achieving a zero power condition whenever a significant line disturbance is encountered.
SUMMARY OF THE INVENTION
The problem identified above is in large part addressed by a circuit designed to provide a low impedance path from Vcc to ground that is activated upon sensing that the Vcc signal has dropped below a specified voltage. During normal operation, the circuit of the present invention maintains an essentially open circuit between Vcc and ground. When the circuit detects an unacceptable drop in Vcc, it drives an output stage coupled between a Vcc bus and ground to a low impedance condition to rapidly dissipate stored charged in the various components of the system. Whether integrated into the system power supply or built into the system motherboard, the present invention assures that system components will settle to 0 V quickly after a power outage thereby minimizing the risk that the system will power up while one or more components are in an indeterminate state.
Broadly speaking, the present invention contemplates an active circuit for rapidly discharging stored energy in a capacitive system. The circuit is comprised of a variable impedance circuit, a voltage detector, and a time delay circuit. The variable impedance circuit includes a variable impedance output path configured to be connected between a Vcc bus of the capacitive system and ground. The voltage detector circuit includes an input coupled to the Vcc bus and an output connected to an input of the variable impedance circuit. The voltage detector circuit is configured to maintain the variable impedance output path in a high impedance condition while the Vcc voltage remains above a predetermined minimum value. The time delay circuit is coupled to the input of the variable impedance circuit and configured to maintain the variable impedance output path in a low impedance condition for a duration after the voltage of the Vcc bus drops below the predetermined minimum.
In one embodiment of the invention, the variable impedance circuit comprises a first transistor including an input terminal and first and second output terminals. In this embodiment, the input terminal of the first transistor is connected to the input of the variable impedance circuit. The first and second output terminals of the first transistor are connected to the Vcc bus and ground respectively. The variable impedance output path comprises a path between the first terminal and the second output terminals. The first transistor is preferably a bipolar transistor, and still more preferably an npn bipolar transistor, in which the transistor base terminal serves as the input terminal, while the emitter and collector terminals serve as the first and second output terminals respectively of the first transistor. In the npn embodiment, the variable impedance output path is maintained in the high impedance condition unless a base-emitter junction of the transistor is forward biased. In this embodiment, the output of the voltage detector circuit prevents the base-emitter junction from becoming forward biased while the voltage of the Vcc bus remains above the predetermined minimum value.
In a presently preferred embodiment, the voltage detector circuit includes a second transistor and a level shifting circuit. The level shifting circuit is tied to the Vcc bus and connected in series between the Vcc bus and an input terminal of the second transistor. The second transistor is preferably a bipolar transistor arranged with the base terminal as the input terminal and the collector terminal as the output of the voltage detector circuit. In this embodiment, the level shifting circuit is preferably comprised of a first resistor tied to Vcc and connected in series to one or more diodes. In an alternative embodiment, the second transistor is a MOS transistor configured with the gate terminal as the input terminal of the second transistor and the drain and source terminals as t

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