Electronic digital logic circuitry – Reliability – Parasitic prevention in integrated circuit structure
Reexamination Certificate
1999-01-12
2001-09-04
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Reliability
Parasitic prevention in integrated circuit structure
C326S030000, C326S082000, C326S101000
Reexamination Certificate
active
06285208
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which delay due to a parasitic capacitance between wiring lines can be reduced.
2. Description of the Related Art
In a conventional semiconductor integrated circuit, various signal wiring lines such as aluminum wiring lines are used to connect between circuit blocks of the semiconductor integrated circuit. The signal wiring lines are always accompanied by parasitic capacities. If the parasitic capacitance is large, the activation speed of the signal wiring line is delayed so that the circuit operation speed becomes slow, or late. As a result, the circuit characteristic of the semiconductor integrated circuit is degraded.
Also, in order to prevent the delay of the circuit operation speed, it is necessary to make an output transistor of a drive circuit sufficiently large such that the parasitic capacitance can be driven sufficiently. As a result, this causes the increase of a chip size and the decrease of a production yield.
The delay due to a parasitic capacitance in the conventional semiconductor integrated circuit will be described with reference to FIG.
1
. In
FIG. 1
, the semiconductor integrated circuit is composed of the buffer circuits B
1
to B
5
and signal wiring lines F
1
to F
5
. The signal wiring lines F
1
to F
5
are arranged in parallel adjacently to each other. The signal wiring lines F
1
to F
5
have wiring line resistances R
1
to R
5
, interline capacitances Cs
12
to Cs
45
between the signal wiring lines and interlayer capacitances Cdf
1
to Cdf
5
between the signal wiring lines and a semiconductor substrate or the ground, respectively. The buffer circuits B
1
to B
5
drive loads (not shown), the wiring line resistances R
1
to R
5
, the interline capacitances Cs
12
to Cs
45
and the interlayer capacitances Cdf
1
to Cdf
5
in response to input signals IN
1
to IN
5
, respectively.
Each interline capacitance Cs
12
to Cs
45
is a capacitance between adjacent wiring lines F
1
to F
5
. Accordingly, the interline capacitance becomes larger as the space between adjacent wiring lines F
1
to F
5
becomes narrow.
Also, the interlayer capacitances Cdf
1
to Cdf
5
are capacitance between the respective signal wiring line F
1
to F
5
and lower wiring lines or a semiconductor substrate. The input signals IN
1
to IN
5
to the buffer circuit B
1
to B
5
are similar to decoded signals and only one of the input signals IN
1
to IN
5
is activated. For example, when the signal IN
2
is a “H (high)” level, the signals IN
1
, IN
3
, IN
4
, IN
5
are set to “L (low)” level. Therefore, when the signal IN
2
of the signals IN
1
to IN
5
is set to the “H” level, only the signal wiring line F
2
is set to the “H” level. All the remaining signal wiring lines F
1
, F
3
, F
4
and F
5
are set to “L” level.
That is, the semiconductor integrated circuit is in the output state {circle around (1)} in which only the signal wiring line F
2
is selected. Next, when the signal IN
4
is set to “H” level in the output state {circle around (1)}, only the signal wiring line F
4
is set to the “H” level. All the remaining signal wiring lines F
1
, F
2
, F
3
and F
5
are set to “L” level. That is, the semiconductor integrated circuit is set to the output state {circle around (2)} in which only the signal wiring line F
4
is selected.
The following table 1 shows a relation of the respective signals and the output states.
TABLE 1
signal wiring
line
output state {circle around (1)}
output state {circle around (2)}
F1
L
L
F2
H
L
F3
L
L
F4
L
H
F5
L
L
As seen from the table 1, when the state of the semiconductor integrated circuit is switched from the output state {circle around (1)} into the output state {circle around (2)}, the signal wiring line F
4
is activated from the “L” level to the “H” level. At this time, the signal wiring line F
2
is switched from the “H” level to the “L” level. However, the signal wiring lines F
3
and F
5
arranged adjacently are fixed to the “L” level. Therefore, the activation speed decreases due to the interline capacitances Cs
34
and Cs
45
, when the signal wiring line F
4
is switched from the inactive state into the active state.
The activation speed of the signal wiring line F
4
is expressed by the following equation (1) using a time constant &tgr;1.
&tgr;1=
R
4
×(
Cs
34
+Cs
45
+Cdf
4
) (1)
As seen from the equation (1), as the interline capacitances Cs
34
and Cs
45
increase, the activation speed becomes slow.
Next, a second conventional example will be described with reference to FIG.
2
. In
FIG. 2
, the second conventional example is different from the first conventional example in that each of shield wiring lines G
1
to G
4
is arranged between corresponding adjacent two of the signal wiring lines F
1
to F
5
shown in FIG.
1
. These shield wiring lines G
1
to G
4
are all fixed to the ground potential GND.
Now, when the state is switched from the output state {circle around (1)} to the output state {circle around (2)} as show in the above table 1, the shield wiring lines G
3
and G
4
function to decrease the influence of coupling noise, which is generated when the signal wiring line F
4
is switched from the “L” level to the “H” level, to the signal wiring lines F
3
and F
5
.
However, the shield wiring lines G
3
and G
4
are fixed to the “L” level. When the signal wiring line F
4
is switched from the “L” level to the “H” level, the activation speed decreases more than the influence of the interline capacitances CG
34
and CG
44
. In this case, the activation speed of the signal wiring line F
4
can be expressed by the following equation (2) using a time constant &tgr;2.
&tgr;2
=R
4
×(
CG
34
+CG
44
+Cdf
4
) (2)
As seen from the equation (2), it could be understood that the activation speed becomes slow as the interline capacitances CG
34
and CG
44
increase.
Next, a third conventional example will be described with reference to FIG.
3
. In the above second conventional example, the shield wiring lines G
1
to G
4
are fixed to the GND potential. However, in the third embodiment, the shield wiring lines V
1
to V
4
are fixed to the power supply voltage Vcc. In this case, the shield wiring lines V
3
and V
4
also function to decrease the influence of coupling noise, which is generated when the signal wiring line F
4
is switched in potential, to the signal wiring lines F
3
and F
5
. However, the activation speed of the signal wiring line F
4
decreases because of the influence of the interline capacitances CV
34
and CV
44
, as in the second conventional example.
Next, the interline capacitance between wiring lines and the structure of the semiconductor integrated circuit will be described with reference to FIG.
4
.
FIG. 4
is a schematic cross sectional view of the semiconductor integrated circuit composed of an insulating film
2
which is formed on a semiconductor substrate
1
and the signal wiring lines F
3
to F
5
provided in the insulating film
2
.
In
FIG. 4
, the signal wiring lines F
3
to F
5
are composed of metal wiring lines such as aluminum wiring lines. Each of the signal wiring lines F
3
to F
5
is electrically separated from the other wiring lines and the semiconductor substrate
1
by the insulating film
2
formed on the semiconductor substrate
1
. Also, a wiring line interval S between every adjacent two of the signal wiring lines F
3
to F
5
is necessary to be made as narrow as possible for high chip integration levels. For this reason, the signal wiring lines F
3
to F
5
are generally arranged to have the wiring line interval S equal to or narrower than the wiring line layer interval d from the main surface of the semiconductor substrate
1
to the signal wiring line F
3
to F
5
. Thus, the wiring line interval S is made narrower with the forming process of fine patterns. Therefore, the interline capacitances Cs
34
and Cs
45
between the wiring li
Chang Daniel D.
Hutchins, Wheeler & Dittmar
NEC Corporation
Tokar Michael
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