Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-03-17
2002-08-13
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06434728
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an activation path simulation equipment and activation path simulation method.
2. Description of the Related Art
Path delay analysis simulation for transistor circuits in designing transistor circuits is now executed for activation patterns at gate level. To determine a critical path by simulation, the activation patterns of a transistor circuit must be obtained.
When all the activation patterns of a path (activation path) from an arbitrary input to output are determined, for example, and if an activation signal is input to an input on the activation path in the transistor circuit where there are n number of inputs, and “0” and “1” are input to the other inputs respectively, 2
n−1
times of simulation are required to obtain all the activation patterns of the transistor circuit.
Depending on the characteristics of the circuit, the setting of “Z” and “inverted value of the activation signal” may also be required in addition to “0” and “1”, to activate the activation path. In this case, the radix of the number of times of simulation increases from 2 to 4, and the number of times of simulation becomes 4
n−1
and, out of the simulation results, a critical path having a maximum or minimum delay must be selected. It is not practical to apply the activation path simulation method requiring such an enormous number of times of simulation to such a transistor circuit as a large-scale integrated circuit (LSI). The problem is the length of processing time required for an enormous number of times of simulation.
On the other hand, such a method as PODEM is known as a method to decrease the number of times of simulation without executing unnecessary simulation, minimizing the activation patterns which do not influence activation, as much as possible, so as to decrease processing time. However, conventional methods target gate level, where decreasing activation patterns is limited, and a further decrease of processing time is desired considering the scale of the current highly dense transistor circuit.
SUMMARY OF THE INVENTION
With the foregoing in view, it is an object of the present invention to provide an activation path simulation equipment and an activation path simulation method which can efficiently determine activation patterns and can further decrease the number of times of simulation.
To achieve the above object, an activation path simulation equipment and an activation path simulation method in accordance with the present invention divides a transistor circuit into a plurality of blocks with reference to the pn junction nodes of the transistors included therein, and the activation patterns are determined for each block using the characteristics of each transistor so as to efficiently create activation patterns of the transistor circuit. In this way, the number of activation patterns to be created can be decreased without creating unnecessary activation patterns, therefore the number of times of simulation can be decreased, which means that simulation speed increases.
To achieve the above object, the activation path simulation equipment of the present invention comprises, for example, a division unit for dividing a transistor circuit into a plurality of blocks with reference to the pn junction nodes in the plurality of transistors constituting the transistor circuit, a creation unit for creating the activation patterns of at least one block on the activation path according to the characteristics of transistors included in the block, and a simulation unit for executing simulation of the activation path according to the created activation patterns.
More specifically, the division unit divides the transistor circuit into blocks according to the power supply node, ground node, and input and output of the transistor circuit, in addition to the above mentioned pn junction nodes. In this way, the transistor circuit is divided into blocks which are the minimum units of activation, and activation patterns at transistor level can be created.
The creation unit creates activation patterns not by using the input of the transistor circuit which does not influence the activation of at least one block on the activation path, but by using the above input which influences thereon. In this way, the creation unit does not consider inputs, which do not influence activation, so that the number of activation patterns decreases and the number of times of simulation decreases.
REFERENCES:
patent: 5920489 (1999-07-01), Dibrino et al.
patent: 5966521 (1999-10-01), Takeuchi et al.
patent: 6223333 (2001-04-01), Kuribayashi et al.
Arayama Masashi
Furuta Eiji
Konno Tadashi
Dinh Paul
Fujitsu Limited
Smith Matthew
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