Activation of CMOS source/drain extensions by ultra-high...

Details Activation of CMOS source/drain extensions by ultra-high... Activation of CMOS source/drain extensions by ultra-high...

2007-06-19

2009-11-10

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Self-aligned

C438S369000, C438S303000

Reexamination Certificate

active

07615458

ABSTRACT:
A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. A dopant is implanted into an extension region of the substrate, with an amount of the dopant remaining in a dielectric layer adjacent the gate electrode. The substrate is annealed at a temperature of about 1000° C. or greater to cause at least a portion of the amount of the dopant to diffuse into the semiconductor substrate.

REFERENCES:
patent: 7033879 (2006-04-01), Hornung et al.
patent: 7078302 (2006-07-01), Ma et al.
patent: 2006/0088969 (2006-04-01), Jain
patent: 2006/0154475 (2006-07-01), Mehrotra et al.
patent: 2006/0199346 (2006-09-01), Jain
patent: 2007/0020900 (2007-01-01), Jain

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