ACS unit in a decoder

Details ACS unit in a decoder ACS unit in a decoder

2006-04-18

2006-04-18

Chase, Shelly (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07032165

ABSTRACT:
A device for implementing a function of add-compare-select type in an error correction code decoder, having first and second adders for adding, respectively for first and second branches, branch metric values, intermediate value of former state metrics, and values of former state metric offset, thus forming first and second values of present state metrics; a comparator, coupled to the first and second adders, for selecting the highest value from among the first and second values; circuitry for determining a digital value of present state metric offset including a single bit, based on the first and second values.

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Boutillon et al. , VLSI Architectures for the MAP Algorithm, Feb. 2003, IEEE Trans. on Comm. vol. 51, No. 2, p. 175-185.

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