Acquisition signal error estimator

Details Acquisition signal error estimator Acquisition signal error estimator

2000-08-31

2003-04-15

Faber, Alan T. (Department: 2651)

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Head amplifier circuit

C360S051000, C360S067000, C360S065000

Reexamination Certificate

active

06549354

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Filed of the Invention
The present invention relates to magnetic recording and, particularly, to an improved error estimator for a sampled amplitude read channel.
2. Description of the Related Art
Sampled amplitude detectors used in magnetic recording require timing recovery in order to correctly extract the digital sequence. As shown in
FIG. 1
, data sectors
100
on magnetic disks are formatted to include an acquisition preamble
102
, a sync or synchronization mark
104
, and user data
106
. Timing recovery uses the acquisition preamble
102
to acquire the correct sampling frequency and phase before reading the user data
106
. The synchronization mark
104
demarcates the beginning of the user data. The preamble
102
is written using the periodic non-return-to-zero (NRZ) sequence 001100110011 . . . which causes the pattern of magnetization SSNNSSNNSSNN . . . to be written on the magnetic medium. The pattern is periodic, having period 4T, where T is the bit period. The pattern is sometimes called a 2T pattern because the interval between successive magnetic field direction transitions is 2T. During the read operation, the sequence of samples [x
i
, x
i+1
, . . .], produced by the preamble is also of period 4T. In the case of PR
4
(partial response) equalization, the sinusoid is ideally sampled at &pgr;/4, 3&pgr;/4, 5&pgr;/4, 7&pgr;/4 and so on, resulting in an equalized sequence of [1, 1, −1, −1, 1, 1, −1, −1, 1, 1, . . .]. In the case of EPR
4
(extended partial response) equalization, the sinusoid is ideally sampled at phases 0, &pgr;/2, &pgr;, 3&pgr;/2 and so on, which results in the equalized sequence [2, 0, −2, 0, 2, 0, −2, 0, 2, 0, . . .]. In the general case of E
2n
PR
4
, where n is a non-negative integer, the sinusoid is ideally sampled at phases &pgr;/4, 3&pgr;/4, 5&pgr;/4, 7&pgr;/4 and so on, resulting in an equalized sequence of [2
n
, 2
n
, −2
n
, −2
n
, 2
n
, 2
n
, −2
n
, −2
n
, . . .]. For E
2n+1
PR
4
equalization, the sinusoid is ideally sampled at phases 0, &pgr;/2, &pgr;, 3&pgr;/2 and so on, which results in the equalized sequence [
2
n+1
, 0, −2
n+1
, 0, 2
n+1
, 0, −2
n+1
, . . .].
Conventionally, the error between the received sample and its ideal value is estimated as x
i
−{overscore (x)}
i
where x
i
is the received sample value and {overscore (x)}
i
is the nearest ideal sample value to the received value x
i
. The nearest ideal sample value {overscore (x)}
i
is computed simply by comparing the received value x
i
to each of the ideal signal levels and declaring {overscore (x)}
i
to be the closest ideal level (i.e., the ideal level that minimizes the absolute value |x
i
−{overscore (x)}
i
| of the error). This is referred to as a slicer or threshold detector estimate.
However, the slicer estimate is disadvantageous in that it is sensitive to distortions in gain, DC offset, and magneto-resistive signal asymmetry. As such, there is a need for an improved error estimator.
SUMMARY OF THE INVENTION
These and other drawbacks in the prior art are overcome in large part by a system and method according to the present invention. An improved system and method for acquisition signal error estimation is provided which uses one or more past values of the sequence to determine the nearest ideal sample value. According to one embodiment, three consecutive samples are used. According to another embodiment, two consecutive samples are used. Finally, according to another embodiment of the invention, consecutive samples are used, but no slicer estimate is required.


REFERENCES:
patent: 4897740 (1990-01-01), Suzuki
patent: 4939685 (1990-07-01), Feintuch
patent: 5379160 (1995-01-01), Otani
patent: 5726818 (1998-03-01), Reed et al.
patent: 5760984 (1998-06-01), Spurbeck et al.
patent: 5812334 (1998-09-01), Behrens et al.
patent: 5835295 (1998-11-01), Behrens
patent: 5892632 (1999-04-01), Behrens et al.
patent: 5909332 (1999-06-01), Spurbeck et al.

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