Chemistry: electrical and wave energy – Processes and products – Coating – forming or etching by sputtering
Reexamination Certificate
2001-07-11
2003-04-29
VerSteeg, Steven H. (Department: 1753)
Chemistry: electrical and wave energy
Processes and products
Coating, forming or etching by sputtering
C204S298020, C204S298060, C427S600000, C427S570000, C427S576000, C118S600000, C118S722000
Reexamination Certificate
active
06554969
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally directed to the field of semiconductor manufacturing, and, more particularly, to acoustically enhanced deposition processes, and systems for performing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
In modern integrated circuit devices, millions of transistors are formed above a surface of a semiconducting substrate. To perform their intended functions, these transistors, or groups of transistors, are electrically coupled together by many levels of conductive inter-connections, i.e., conductive metal lines and plugs. These conductive lines and plugs allow electrical signals to propagate throughout the integrated circuit device. In general, these conductive interconnections are formed in layers of insulating material, e.g., silicon dioxide, HSQ, or other materials that may have a dielectric constant less than approximately 5.0. The insulating materials electrically isolate the various conductive interconnections and tend to reduce capacitive coupling between adjacent metal lines when the integrated circuit device is in operation. As the demand for high performance integrated circuit devices continues to increase, circuit designers and manufacturers look for ways to improve device performance. Recently, copper has become the material of choice for conductive interconnections for high performance integrated circuit devices, e.g., microprocessors, due to its lower resistance as compared to, for example, aluminum.
Conductive interconnections comprised of copper may be formed using a variety of process flows, e.g., single damascene, dual damascene, etc. For example, a layer of insulating material may be formed on or above a semiconducting substrate. Thereafter, a plurality of openings may be formed in the layer of insulating material using known photolithographic and etching techniques. Then, a relatively thin barrier metal layer comprised of, for example, tantalum, is conformally deposited above the insulating layer and in the openings in the insulating layer. Next, a relatively thin layer of copper, a so-called copper seed layer, is deposited on the barrier metal layer. A much thicker layer of copper is then formed by using known electroplating techniques. This final layer of copper will fill the remaining portions of the openings in the insulating layer, and have an upper surface that extends above the surface of the insulating layer. Ultimately, one or more chemical mechanical polishing (CMP) operations will be performed to remove the excess copper and barrier layer material from above the surface of the insulating layer. This process results in the definition of a plurality of conductive interconnections, e.g., conductive lines or plugs, or a combination of both, positioned within the openings in the insulating layer.
In the fabrication of semiconductors and other electronic devices, the directionality of the particles being deposited, e.g., metal particles, is important in filling small openings. As circuit densities increase, the widths of vias, contacts and other features have decreased to 0.25 &mgr;m or less, whereas the thicknesses of the dielectric layers remain substantially constant. Thus, the aspect ratios for the openings or features, i.e., the ratio of the depth to the minimum lateral dimension, increases, thereby pushing the aspect ratios of the contacts and vias to 4:1 and above. As the dimensions of the openings decrease, it becomes even more important to get directionality of the deposited particles in order to achieve conformal coverage on the sidewalls and bottom of the opening.
Conventional physical vapor deposition (PVD) processes are not well suited for directional deposition and, therefore, have difficulty penetrating and conformally lining the sidewalls and bottoms of openings where the aspect ratio exceeds 4:1. Thus, the uniformity and step coverage of the deposited layer will depend directly upon the structure architecture with the layer becoming thinner on the structure bottom and sidewall near the bottom. The uniformity and step coverage of the layer, and therefore the integrity of the layer, may be compromised by overhangs, voids and other undesirable formations in the device features.
To deposit material in high aspect ratio openings, methods such as a medium/high pressure physical vapor deposition (PVD) process, an ionized metal plasma (IMP) process, or a high density plasma physical vapor deposition (HDP-PVD), may be employed. The plasma density in IMP processes are typically between about 10
11
cm
−3
and 10
12
cm
−3
. Generally, IMP processing offers the benefit of highly directional deposition with good bottom coverage in high aspect ratio openings. Initially, a plasma is generated by introducing a gas, such as helium or argon, into the chamber and then biasing a target to produce an electric field in the chamber, thereby ionizing a portion of the gas. An energized coil positioned proximate the processing region of the chamber couples electromagnetic energy into the plasma to result in an inductively-coupled medium/high density plasma between the target and a susceptor on which a substrate is placed for processing. The ions and electrons in the plasma are accelerated toward the target by the bias applied to the target causing the sputtering of material from the target. Under the influence of the plasma, the sputtered metal flux is ionized. An electric field due to an applied or self-bias, develops in the boundary layer, or sheath, between the plasma and the substrate that accelerates the metal ions towards the substrate in a direction substantially parallel to the electric field and perpendicular to the substrate surface. The bias energy is preferably controlled by the application of power, such as RF, to the susceptor to attract the sputtered target ions in a highly directionalized manner to the surface of the substrate to fill the features formed on the substrate.
The high density plasma of conventional HDP-PVD is typically achieved by operating at pressures between about 5-100 mTorr. It is believed that such pressures ensure thermalization and ionization of the sputtered metal particles. Thermalization refers to the slowing of the metal particles passing through the plasma by collisions with the plasma ions and must be sufficiently high to allow time for the coil to ionize the metal particles. Should the metal particles travel from the target to the substrate too quickly, the metal particles may not be ionized resulting in poor deposition rates and uniformity. Some of the problems encountered in forming metal layers in integrated circuit devices, and illustrative processes for forming such layers, are set forth in U.S. Pat. Nos. 6,200,433 B1, 6,238,533 B1 and 6,236,163 B1, each of which are hereby incorporated by reference in their entirety. Problems, such as voids or overlays, still exist with respect to forming layers of material, e.g., a metal, in openings having high aspect ratios. This is particularly true with respect to the formation of barrier metal layers and copper seed layers in integrated circuit devices.
The
Advanced Micro Devices , Inc.
VerSteeg Steven H.
Williams Morgan & Amerson
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