Achieving page hit memory cycles on a virtual address reference

Details Achieving page hit memory cycles on a virtual address reference Achieving page hit memory cycles on a virtual address reference

1998-06-05

2001-05-01

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S200000, C711S205000, C711S206000

Reexamination Certificate

active

06226730

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to virtual addressing, and more particularly to reducing the amount of time required to access memory in response to a virtual address reference.
BACKGROUND OF THE INVENTION
Many modern computer systems use virtual addressing to hide the underlying complexity of their physical address spaces. A virtual address is an address that must be translated into a physical address before it can be used to access memory. By presenting a computer system's operating memory as a virtual address space, the operating memory may be made to appear larger or less fragmented than it actually is. For example, in a computer system that has a 32 MB (mega-byte) operating memory, an even larger virtual memory may be presented for use by application programs by mapping portions of the virtual memory to a storage other than the operating memory (e.g., a disk drive). If necessary, regions of the virtual address space can be dynamically remapped from a relatively slow mass storage device to operating memory. Also, a physical operating memory that has gaps of unused physical address space (i.e., a fragmented memory) can be made to appear as a contiguous address space in the virtual realm.
One important application of virtual addressing is the storage and retrieval of graphics objects, such as textures, depth information and color information, in operating memory. Because graphics objects are often used to provide real-time visual effects, it is important that graphics objects be retrieved from memory quickly and without spending excessive time translating their virtual address references.
In many computer systems, virtual addresses are translated into physical addresses by a processor (or other bus master) before the processor issues memory access requests to a memory controller. In other computer systems, at least some virtual-to-physical address translation is performed in the memory controller. Performing address translation in the memory controller centralizes the address translation activity and allows virtual addressing to be used by subsystems in the computer system that do not have address translation capability.
One technique for performing a virtual-to-physical address translation in a memory controller is for the memory controller to use incoming virtual addresses to index a lookup table in operating memory. The lookup table is initialized with physical addresses during system startup so that, when indexed using a virtual address, the corresponding physical address is returned to the memory controller. Unfortunately, this technique requires the memory controller to access memory twice in response to a single memory access request; one memory access to retrieve a physical address and a second memory access to operate on the memory location indicated by the physical address. The extra memory access required to retrieve the physical address from the lookup table significantly slows the overall response to the original memory access request.
One technique for avoiding the need to access a lookup table in response to a virtual address is to buffer recently used physical addresses in the memory controller. When a virtual address is received, it is compared against previously received virtual addresses to determine if a corresponding physical address has been buffered. If a corresponding physical address has been buffered, then the access to the address lookup table is unnecessary and the buffered physical address can be used to access the memory location of interest.
Although buffering physical addresses in the memory controller improves memory access time in response to virtual addresses, substantial time is still usually required (e.g., one or two clock cycles) to determine whether a needed physical address has been buffered in the memory controller. The amount of time required increases with the size of the buffer. Because virtual addressing is often used to perform time critical memory accesses such as retrieval of graphics object information, any reduction in the time required to resolve a virtual address to a physical location in the memory subsystem can significantly increase the overall performance of the computer system.
SUMMARY OF THE INVENTION
An apparatus and method for accessing a memory are disclosed. A source address is received that includes a page address and a page offset. The page address requires translation in order to form a first address that can be used to transfer data from a row of memory cells into a sense amplifier array in a memory. The page address is compared to contents of one or more page registers to determine if the data is present in the sense amplifier array as a result of a previous memory access. If the data is determined to be present in the sense amplifier array, a second address is asserted to access a portion of the data.
Other features and advantages of the invention will be apparent from the accompanying drawings and from the detailed description that follows below.


REFERENCES:
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patent: 5475827 (1995-12-01), Lee et al.
patent: 5561778 (1996-10-01), Fecteau et al.
patent: 5566308 (1996-10-01), Bendelac et al.
patent: 5594881 (1997-01-01), Fecteau et al.

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