Achieving fast parasitic closure in a radio frequency...

Details Achieving fast parasitic closure in a radio frequency... Achieving fast parasitic closure in a radio frequency...

2004-11-24

2010-06-08

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C703S002000

Reexamination Certificate

active

07735048

ABSTRACT:
Methods achieve fast parasitic closure in IC (integrated circuit) synthesis flow with particular application to RFIC (radio frequency integrated circuit) synthesis flow. Parasitic corners generated based on earlier layout statistics are incorporated into circuit resizing to enable parasitic robust designs. The worst-case parasitic corners are generated efficiently without expensive statistical computations. A performance-driven placement with simultaneous fast rough routing and device tuning generates high quality placements and compensates for layout induced performance degradations. A regression-tree based macromodeling methodology is introduced for modeling of electrical performances to enable true performance-driven layout synthesis. To improve sampling quality, an annealing-based placer can be used to perform sampling. The modeling methodology can be adapted to include automatically adjusting the device tuning ranges to meet certain model accuracy requirements.

REFERENCES:
patent: 4827428 (1989-05-01), Dunlop et al.
patent: 5548539 (1996-08-01), Vlach et al.
patent: 5751593 (1998-05-01), Pullela et al.
patent: 5754826 (1998-05-01), Gamal et al.
patent: 5764532 (1998-06-01), Patel
patent: 5787008 (1998-07-01), Pullela et al.
patent: 5790436 (1998-08-01), Chen et al.
patent: 5896300 (1999-04-01), Raghavan et al.
patent: 5987086 (1999-11-01), Raman et al.
patent: 6018623 (2000-01-01), Chang et al.
patent: 6209123 (2001-03-01), Maziasz et al.
patent: 6272668 (2001-08-01), Teene
patent: 6282693 (2001-08-01), Naylor et al.
patent: 6286126 (2001-09-01), Raghavan et al.
patent: 6353917 (2002-03-01), Muddu et al.
patent: 6374395 (2002-04-01), Wang
patent: 6430729 (2002-08-01), Dewey et al.
patent: 6588002 (2003-07-01), Lampaert et al.
patent: 6591402 (2003-07-01), Chandra et al.
patent: 6725438 (2004-04-01), van Ginneken
patent: 6751744 (2004-06-01), Allen et al.
patent: 6789248 (2004-09-01), Lu et al.
patent: 6901570 (2005-05-01), Lu
patent: 7003745 (2006-02-01), Subasic et al.
patent: 7137097 (2006-11-01), Aji et al.
patent: 7206731 (2007-04-01), Sercu et al.
patent: 7243320 (2007-07-01), Chiu et al.
patent: 7331029 (2008-02-01), Amit et al.
patent: 7340698 (2008-03-01), Srinivasan et al.
patent: 7356784 (2008-04-01), Dengi et al.
patent: 7360191 (2008-04-01), Chang et al.
patent: 7480605 (2009-01-01), Angyal et al.
patent: 2002/0104063 (2002-08-01), Chang et al.
patent: 2003/0188280 (2003-10-01), Lu
patent: 2004/0167756 (2004-08-01), Yonezawa
patent: 2007/0124707 (2007-05-01), Sutjahjo et al.
Aktuna, Mehmet et al. (Apr. 1999) “Device-Level Early Floorplanning Algorithms for RF Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(4): 375-388.
Breiman et al. (1984) “Regression Trees,” and “Bayes Rules and Partitions,” Chapters 8 and 9 In,Classification and Regression Trees, Peter J. Bickel, et al. eds., Wadsworth International Group; Belmont, California, pp. v-vii (table of contents) and pp. 216-278.
Charbon, Edoardo et al. (1992) “A Constraint-Driven Placement Methodology for Analog Integrated Circuits,” IEEE 1992 Custom Integrated Circuits Conference, 28.2.1-28.2.4.
Cohn, John M. et al. (Mar. 1991) “Koan/Anagram II: New Tools for Device-Level Analog Placement and Routing,” IEEE Journal of Solid-State Circuits, 26(3): 330-342.
Daems, Walter et al. (Nov. 2001) “Simulation-based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing,” ACM/IEEE ICCAD, pp. 70-74.
Dharchoudhury, Abhijit et al. (Apr. 1995) “Worst-Case Analysis and Optimization of VLSI Circuit Performances,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 14(4): 481-492.
Eshbaugh, Kevin S. (Oct. 1992) “Generation of Correlated Parameters for Statistical Circuit Simulation,” IEEE Transactions on Computer-Aided Design, 11(10): 1198-1206.
Gielen, Georges G. E. et al. (Dec. 2000) “Computer-Aided Design of Analog and Mixed-Signal Integrated Circuits,” Proceedings of the IEEE, 88(12): 1825-1852.
Ivakhnenko, A. G. (Oct. 1971) “Polynomial Theory of Complex Systems,” IEEE Transactions on Systems, Man, and Cybernetics, SMC-1(4) 364-378.
Krasnicki, Michael et al. (Jun. 1999) “Maelstrom: Efficient Simulation-Based Synthesis for Custom Analog Cells,” Proceedings ACM/IEEE Design Automation Conference, 6 pages.
Lampaert, Koen et al. (Jul. 1995) “A Performance-Driven Placement Tool for Analog Integrated Circuits,” IEEE Journal of Solid-State Circuits, 30(7): 773-780.
Liu, Hongzhou et al.. (Jun. 2002) “Remembrance of Circuits Past: Macromodeling by Data Mining in Large Analog Design Spaces,” IEEE/ACM DAC 2002, pp. 437-442.
Lokanathan, A. N. et al. (1995) “Efficient Worst Case Analysis of Integrated Circuits,” Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, pp. 237-240.
Low, K. K. et al. (Jul. 1991) “A New Methodology for Design Centering of IC Fabrication Processes,” IEEE Transactions on Computer-Aided Design, 10(7): 895-903.
Sait, Sadiq M. et al. (1995),VLSI Physical Design Automation: Theory and Practice, IEEE Press, Piscataway, New Jersey, USA, pp. 211-223.
Spectre RF User's Manual, Cadence Design Systems, San Jose, California, Jun. 2003, pp. 1-112.
Vancorenland, P. et al. (2001) “A Layout-aware Synthesis Methodology for RF Circuits,” IEEE ICCAD, pp. 358-362.
Worsham, A. Hodge et al. (2002) “A Parasitic-Aware Synthesis-Based Analog Design Flow,” 2002 IEEE Custom Integrated Circuits Conference, May 12-15, 2002, Orlando, Florida, 4 pages.
Wyss, Gregory D. et al. (Feb. 1998),A User's Guide to LHS: Sandia's Latin Hypercube Sampling Software, Sandia National Laboratories, Albuquerque, New Mexico, USA, entire document.
Zhang, Gang (May 2004),An RF Synthesis Flow Toward Fast Parasitic Closure, Ph.D. Dissertation, Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania, USA, entire document.

Affiliated with

Also associated with

Rating

Achieving fast parasitic closure in a radio frequency... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Achieving fast parasitic closure in a radio frequency..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Achieving fast parasitic closure in a radio frequency... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4170798