Electrical computers and digital data processing systems: input/ – Access locking
Reexamination Certificate
2007-01-23
2009-02-03
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Access locking
C710S240000, C710S244000
Reexamination Certificate
active
07487279
ABSTRACT:
A method for implementing a spin lock in a system including a plurality of processing nodes, each node including at least one processor and a cache memory, the method including steps of: acquiring exclusivity to the cache memory; checking the availability of the spin lock; setting the spin lock to logical one if the spin lock is available; setting the spin lock to logical zero once processing is complete; and explicitly yielding the cache memory exclusivity. Yielding the cache memory exclusivity includes instructing the cache coherent hardware to mark the cache memory as non-exclusive. The cache memory is typically called level two cache.
REFERENCES:
patent: 5442763 (1995-08-01), Bartfai et al.
patent: 6260117 (2001-07-01), Freerksen et al.
patent: 6275907 (2001-08-01), Baumgartner et al.
patent: 6779090 (2004-08-01), McKenney et al.
patent: 6792497 (2004-09-01), Gold et al.
patent: 7246187 (2007-07-01), Ezra et al.
Definition of Cache Coherency from Wikipedia, undated.
T.E. Anderson, The Performance Implications of Spin Lock Alternatives for Shared-Memory Multiprocessors. IEEE Transaction on Parallel and Distributed Systems, 1(1):6-16, Jan. 1990.
J.M. Mellor-Crummey and M.L. Scott, Algorithms for Scalable Synchronization on Shared-Memory Multiprocessors. ACM Transactions on Computer Systems, 9(1):21-65, Feb. 1991.
B.-H. Lim and A. Agarwal, Reactive Synchronization Algorithms for Multiprocessors. ASPLOS 1994.
S. Swaminathan, J. Stultz, J.F. Vogel, P. McKenney, Fairlocks—A High Performance Fair Locking Scheme. 14th International Conference on Parallel and Distributed Computing and Systems, Nov. 2002.
Buchenhorner Michael J.
Cameron Douglas W.
Dang Khanh
International Business Machines - Corporation
LandOfFree
Achieving both locking fairness and locking performance with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Achieving both locking fairness and locking performance with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Achieving both locking fairness and locking performance with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4056873