Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2011-01-25
2011-01-25
Doan, Nghia M (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C703S013000, C703S014000
Reexamination Certificate
active
07877717
ABSTRACT:
Mechanisms for accurately modeling an asynchronous interface using expanded logic elements are provided. With these mechanisms, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanisms of the present invention to take into consideration whether or not the primitive logic elements themselves may be experiencing a switching or glitch hazard and whether or not the inputs to the primitive logic elements may be based on a switching or glitch hazard from another primitive logic element in the asynchronous interface logic. These expanded logic elements are used in an integrated circuit design to replace the original primitive logic elements in the design. The asynchronous interface may then be simulated with the expanded logic elements providing outputs indicative of whether the actual data output of the expanded logic elements is deterministic or not.
REFERENCES:
patent: 4979190 (1990-12-01), Sager et al.
patent: 5469367 (1995-11-01), Puri et al.
patent: 5493505 (1996-02-01), Banerjee et al.
patent: 5592685 (1997-01-01), Pawlowski
patent: 5748487 (1998-05-01), Sawasaki et al.
patent: 5790830 (1998-08-01), Segal
patent: 5886904 (1999-03-01), Dai et al.
patent: 6226774 (2001-05-01), Sawasaki et al.
patent: 6321184 (2001-11-01), Baumgartner et al.
patent: 6321366 (2001-11-01), Tseng et al.
patent: 6324679 (2001-11-01), Raghunathan et al.
patent: 6785873 (2004-08-01), Tseng
patent: 6892314 (2005-05-01), Chen
patent: 6956788 (2005-10-01), Nguyen et al.
patent: 6957403 (2005-10-01), Wang et al.
patent: 7089518 (2006-08-01), Bair et al.
patent: 7299436 (2007-11-01), Chu et al.
patent: 7395469 (2008-07-01), Anderson et al.
patent: 2005/0069068 (2005-03-01), Gundurao et al.
patent: 2006/0190858 (2006-08-01), Chu et al.
Unger, Stephen, “Hazards, Critical Races, and Metastability”, IEEE, vol. 44, No. 6, Jun. 1995, pp. 754-768.
Lavagno et al., “Algorithms for synthesis of hazard-free asynchronous circuits”, ACM, 1991, pp. 302-308.
Shieh et al., “Fault effects in asynchronous sequential logic circuits”, IEEE, vol. 140, No. 6, Nov. 1993, p. 327-332.
Lin et al., “Synthesis of Hazard-Free Multi-level Logic under Multiple-Input Changes from Binary Decision Diagrams”, IEEE/ACM, 1994, pp. 542-549.
U.S. Appl. No. 10/841,729, Image File Wrapper printed Sep. 2, 2010, 1 page.
U.S. Appl. No. 11/054,880, Image File Wrapper printed Sep. 2, 2010, 2 pages.
Chu Bing-Lun
Ja Yee
Nelson Bradley S.
Roesner Wolfgang
Baca Matthew W.
Doan Nghia M
International Business Machines - Corporation
Walder, Jr. Stephen J.
LandOfFree
Accurately modeling an asynchronous interface using expanded... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Accurately modeling an asynchronous interface using expanded..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Accurately modeling an asynchronous interface using expanded... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2640724