Accurate wire load model

Details Accurate wire load model Accurate wire load model

2001-11-20

2004-07-13

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06763503

ABSTRACT:

BACKGROUND OF INVENTION
A typical integrated circuit contains millions of electrical components such as transistors, resistors, capacitors, diodes, and their associated interconnections, which are usually made through conductive materials made of deposited metal, polysilicon, and the like. An integrated circuit's components and their interconnections are typically arranged in a plurality of metal layers which are formed over a substrate typically formed by a silicon wafer. Each layer can contain several thousand conductors. Such conductors are typically electrically insulated from one another by a non-conducting material or dielectric material such as borophosphosilicate glass, silicon dioxide, and the like.
FIG. 1
shows a section of a typical semiconductor wafer (
10
) having a substrate (
12
) and a plurality of conductors (
14
,
16
,
18
,
20
). The conductors (
14
,
16
,
18
,
20
) are separated from one another and insulated by dielectric material layers (
22
,
24
). The vertical and lateral spacing of the conductors (
14
,
16
,
18
,
20
) can lead to a phenomenon known as “parasitic capacitance.” Capacitance is a natural phenomenon that exists between any two conductors that are not electrically connected to each other; the shorter the distance between two conductors, the larger the capacitance. Parasitic capacitance is termed as such because it is an undesirable effect resulting from the close proximity of conductors in an integrated circuit.
In
FIG. 2
, exemplary parasitic capacitances are schematically shown as capacitor elements that are joined between the conductors (
14
,
16
,
18
,
20
), where the conductors (
14
,
16
,
18
,
20
) are shown for clarity without dielectric material layer boundaries. To calculate, or otherwise determine, the parasitic capacitance attributed to an integrated circuit conductor, the parasitic capacitance can be broken down into components, as modeled in FIG.
2
. Particularly, three different components of parasitic capacitance are shown: area capacitance (C
a
), a coupling or lateral capacitance (C
c
), and a fringing or fringe capacitance (C
f
).
The area capacitance, C
a
, is the component of parasitic capacitance that exists between the top and bottom surface of two overlapping conductors. Accordingly, portions of the top surface of conductor (
14
) are overlapped by portions of the bottom surface of conductor (
16
). Hence, parasitic area capacitance can develop therebetween.
Lateral coupling capacitance, C
c
, is the component of parasitic capacitance that exists between adjacent lateral edges of two conductors. Accordingly, the adjacent lateral edges of conductors (
16
,
18
) can give rise to the shown coupling capacitance.
Fringe capacitance, C
f
, also known as “edge capacitance,” is the component of parasitic capacitance that exists between a lateral edge of a first conductor and either the top or bottom surface of a second conductor that overlaps, or underlaps, the lateral edge of the first conductor. Accordingly, the leftmost side edge of conductor (
16
) and the top of conductor (
14
) can give rise to a fringe capacitance. The fringe capacitance is essentially a distortion to the area capacitance component causes by fringing effects at a conductor's lateral edges. Similarly, as shown in
FIG. 2
, there are area and fringe components of capacitance between metals and the semiconductor substrate (
12
).
An undesirable effect of parasitic capacitance is to slow the propagation of electrical signals through a circuit, thereby reducing the speed at which an integrated circuit can operate. The larger the parasitic capacitance, the greater the delay a signal will encounter as it travels through a conductor. If the components of parasitic capacitance can be extracted from an integrated circuit from the integrated circuit's physical design, such components can be used to estimate the delay for signals in the integrated circuit through a process known as “timing and noise analysis.” This information can then be used to adjust the physical layout of the conductors in an integrated circuit, thereby improving the performance of an integrated circuit.
Typically, within the integrated circuit industry, there are a number of extraction tools, e.g., layout parasitic extractors, that are designed to enable circuit designers to extract and analyze parasitic capacitances. Often, because such parasitic extraction is performed during an early circuit design stage that is prior to the actual layout of the integrated circuit, designers rely on “wire load models” in order to conduct their timing and noise analyses. Thus, due to the earliness of the parasitic extraction stage in the design cycle, the layout of the circuit is typically not yet available, and therefore, designers use general topological structures, such as the one shown in
FIG. 1
, for timing and noise analyses.
In conventional wire load models, capacitance is a function of wire width, spacing, layer thickness, and interlayer thickness. Such models use general formulas that conform to normal circuit conditions. However, these formulas tend to yield inaccurate findings with reference to real applications because the formulas are formed by consideration of certain layers when certain conditions are true. Further, conventional wire load models may not account for the different kinds of dielectric materials that are used in semiconductor technologies. In other words, previous models are not generic enough for all metal configurations because they are based on relatively simple geometric configurations. Moreover, such models are heavily dependent on technology and have to be redesigned/remodeled as technology changes.
SUMMARY OF INVENTION
According to one aspect of the present invention, a method for creating a wire load model comprises creating an interconnect configuration, running a field solver to generate parasitic information for the interconnect configuration, storing the parasitic information in an accessible format, and running a curve-fitting engine to create the wire load model, where running the curve-fitting engine is dependent on the parasitic information.
According to another aspect, a program storage device readable by a machine that tangibly embodies a program of instructions executable by the machine to perform a method for creating a wire load model comprises creating a wire structure, running a field solver to generate parasitic information for the wire structure, storing the parasitic information in an accessible format, and running a curve-fitting engine to create the wire load model, where running the curve-fitting engine is dependent on the parasitic information.
According to another aspect, a computer system comprises a memory for storing a model of a circuit, a processor for creating a wire load model (where the processor establishes an interconnect configuration for the circuit), a field solver for determining parasitic information for the interconnect configuration, and a curve-fitting engine that uses the parasitic information to generate the wire load model.
According to another aspect, a method for creating a wire load model comprises creating an interconnect configuration, generating parasitic information for the interconnect configuration, storing the parasitic information in an accessible format, and creating the wire load model dependent on the parasitic information.
According to another aspect, a wire load model creation tool comprises means for creating an interconnection configuration for a structure, means for field solving the interconnect configuration to determine parasitic information, means for storing the parasitic information, curve-fitting means for curve-fitting the parasitic information and using interconnect configuration parameters to create a wire load model, and means for controlling error in the curve-fitting means.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 5610833 (1997-03-01), Chang et al.
patent: 5629860

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