Data processing: measuring – calibrating – or testing – Measurement system – Dimensional determination
Reexamination Certificate
2001-02-07
2003-06-17
Bui, Bryan (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system
Dimensional determination
C702S150000, C702S155000, C382S145000
Reexamination Certificate
active
06581023
ABSTRACT:
FIELD OF THE INVENTION
The present specification is related to integrated circuit (IC) fabrication. More specifically, the present specification is related to measuring the critical dimension (CD) of an integrated circuit feature using a variable threshold process.
BACKGROUND OF THE INVENTION
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to put millions of devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC.
One limitation to the smallness of IC critical dimensions is conventional lithography. In general, projection lithography refers to processes for pattern transfer between various media. According to conventional projection lithography, a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film or coating, the photoresist. An exposing source of radiation (such as light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The lithographic coating is generally a radiation-sensitized coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern.
Exposure of the coating through a photomask or reticle causes the image area to become selectively crosslinked and consequently either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble (i.e., uncrosslinked) or deprotected areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
Projection lithography is a powerful and essential tool for microelectronics processing. As feature sizes are driven smaller and smaller, optical systems are approaching their limits caused by the wavelengths of the optical radiation.
One alternative to projection lithography is EUV lithography. EUV lithography reduces feature size of circuit elements by lithographically imaging them with radiation of a shorter wavelength. “Long” or “soft” x-rays (a.k.a., extreme ultraviolet (EUV)), wavelength range of lambda=50 to 700 angstroms are used in an effort to achieve smaller desired feature sizes.
In EUV lithography, EUV radiation can be projected onto a resonant-reflective reticle. The resonant-reflective reticle reflects a substantial portion of the EUV radiation which carries an IC pattern formed on the reticle to an all resonant-reflective imaging system (e.g., series of high precision mirrors). A demagnified image of the reticle pattern is projected onto a resist coated wafer. The entire reticle pattern is exposed onto the wafer by synchronously scanning the mask and the wafer (i.e., a step-and-scan exposure).
Although EUV lithography provides substantial advantages with respect to achieving high resolution patterning, errors may still result from the EUV lithography process. For instance, the reflective reticle employed in the EUV lithographic process is not completely reflective and consequently will absorb some of the EUV radiation. The absorbed EUV radiation results in heating of the reticle. As the reticle increases in temperature, mechanical distortion of the reticle may result due to thermal expansion of the reticle.
Both conventional projection and EUV lithographic processes are limited in their ability to print small features, such as, contacts, trenches, polysilicon lines or gate structures. As such, the critical dimensions of IC device features, and, thus, IC devices, are limited in how small they can be.
Critical dimensions can be measured using a scanning electron microscope (SEM). Measurements of critical dimensions of integrated circuit features can be inaccurate due to limitations of the SEM. For example, a measurement of the critical dimension at the bottom of a trench formed for a contact can measure larger than actual by the SEM at defocus conditions. Inaccurate measurements such as this make accurate depth of focus margins difficult because true values are not known.
Thus, there is a need for a process of measuring critical dimensions of integrated circuit features which is more accurate. Further, there is a need for a method of correctly identifying the width of a contact hole. Yet further, there is a need for a method of determining depth of focus margins more accurately. Even further still, there is a need for a system for measuring critical dimensions of integrated circuit features more accurately than a conventional SEM measurement.
SUMMARY OF THE INVENTION
An embodiment is related to a method of measuring the critical dimension of an integrated circuit feature using a variable threshold process. This method can include obtaining a first slope measurement of lateral side walls of an integrated circuit feature at best focus conditions, obtaining a second slope measurement of lateral side walls of the integrated circuit feature at defocus conditions, and calculating a critical dimension of the integrated circuit feature from the first slope measurement and the second slope measurement.
Another embodiment is related to a method of using a scanning electron microscope to measure a critical dimension of an integrated circuit feature. This method can include determining a slope &agr; of a contact hole at best focus conditions, determining a slope &bgr; of the contact hole at defocus conditions, and, using the slope &agr; and the slope &bgr;, determining a critical dimension (CD) at a bottom of an integrated circuit feature.
Another embodiment is related to a variable threshold method of accurately determining a critical dimension (CD) of an integrated circuit feature. This method can include applying a scanning electron microscope (SEM) to an aperture in a layer of material in a portion of an integrated circuit, obtaining a first measurement of a critical dimension of the aperture, applying the SEM again to the aperture, obtaining a second measurement of the critical dimension of the aperture; and determining a depth of focus margin using the first measurement and the second measurement.
Other principle features and advantages of the present invention will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims.
REFERENCES:
patent: 5969273 (1999-10-01), Archie et al.
patent: 6178256 (2001-01-01), Nguyen et al.
patent: 6185323 (2001-02-01), Archie et al.
patent: 6208747 (2001-03-01), Nguyen et al.
patent: 6277661 (2001-08-01), Yang et al.
Advanced Micro Devices , Inc.
Bui Bryan
Foley & Lardner
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