Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-02-14
2008-11-11
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
07451367
ABSTRACT:
A system and method for executing a sequential data memory access through a serial access port is provided. The system may include a memory access controller to receive a block access command and successively access data elements in the block. In certain implementations, a test device, such as a JTAG host, transmits a block read or write command specifying a start address and an increment value to an embedded device under test, whereupon a memory access controller in the embedded device sequentially accesses the data at the start address, increments the address by the increment value, accesses the data at the incremented address, and repeats this procedure to sequentially access each of the remaining data elements in the block.
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“IEEE Standard Test Access Port and Boundary-Scan Architecture” IEEE Std 1149.1-2001 (Revision of IEEE Std 1149.1-1990) 208 pages.
Non-final Office Action, mailed Apr. 4, 2008, U.S. Appl. No. 11/353,873, 18 pages.
ATMEL Corporation
Fish & Richardson P.C.
Kerveros James C
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