Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2002-05-31
2004-11-30
Elmore, Stephen (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S213000, C711S137000, C711S154000, C711S156000, C711S163000, C711S204000, C713S322000, C713S601000
Reexamination Certificate
active
06826670
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to techniques for accessing memory units in a data processing apparatus.
2. Description of the Prior Art
A data processing apparatus will typically include a processor core for executing data processing operations. A memory system will then be made available to the processor core for storing data and/or instructions required by the processor core to perform such data processing operations. Hence, the processor core will receive instructions and associated data from the memory system, will execute those instructions, and optionally will output data for storing back in the memory system. Hereafter, the term “data value” will be used to refer to both instructions and data. When a data value is to be transferred to/from the memory system, the processor core will issue an access request specifying that transfer.
A typical memory system will include a main memory, also referred to herein as an external memory, which can store the data values required by the processor core. However, the retrieval of data values from that main memory, and the writing of data values back to that main memory, is typically a relatively slow process, and accordingly it is known to provide one or more memory units in addition to the main memory within the memory system. A well-known example of such an additional memory unit is a cache, which can be used to store data values retrieved from the main memory, and/or data values output by the processor core, so that those data values are readily available to the processor core if required for subsequent data processing operations. It will be appreciated by those skilled in the art that there are a number of well-known techniques for determining which data values get stored within the cache, and which data values get evicted from the cache when new data values need storing within the cache. However, fundamentally, the cache is typically relatively small compared to the main memory, is significantly quicker to access than the main memory, and is aimed at temporarily storing data values that are likely to be needed by the processor core.
The memory system may include a single cache, or alternatively may contain a plurality of caches arranged, for example, in a hierarchical structure.
In addition, another type of memory unit that may be included within the memory system is a tightly-coupled memory (TCM), which is typically connected to the processor bus on which the processor core issues access requests, and is used to store data values for which a deterministic access time is required. The TCM presents a contiguous address space to a programmer, which can be used to store data values, and hence, as an example, a particular portion of code for which a deterministic access time is important can be stored directly in the TCM. The TCM can be used as if it were a particular portion of the main memory (i.e. the data values in the TCM are not replicated in the main memory), or alternatively the data values to be placed in the TCM can be copied from the main memory. Typically, a register somewhere within the data processing apparatus will keep a record of the address range of data values placed in the TCM so that it can be determined whether a particular data value the subject of an access request by the processor core will be found in the TCM or not. The TCM may be embodied in any appropriate form, for example, Random Access Memory (RAM), Read Only Memory (ROM), etc.
In a data processing apparatus of the above type, where the memory system comprises a plurality of memory units, an access request issued by a processor core is typically analysed to determine which memory unit should be used to perform the access. For example, if the access request relates to a read of a data value, and the address issued as part of the access request relates to a cacheable area of memory, then it is appropriate to access the cache to determine whether that data value is present in the cache. If it is, then the data value can be returned directly to the processor core, whereas if it is not, then typically a linefill procedure will be invoked to read a number of data values, including the data value of interest, from external memory, and to then place those retrieved data values in a line of the cache.
Similarly, if having reference to the register storing the address range of data values stored in the TCM, it is determined that the data value resides in the TCM, then it is clearly appropriate to access the TCM to retrieve the data value required by the processor core.
However, to achieve desired performance levels for performing accesses, there is not typically sufficient time to wait for the above-described analysis of the access request to be completed before the access to the appropriate memory unit is initiated. Instead, for performance reasons, it is typically required to simultaneously perform the access to multiple of the memory units, so that by the time the analysis of the access request has taken place, and the appropriate memory unit to access has hence been determined, that memory unit is already in a position to complete the access (for example by outputting the desired data value to the processor core for a read request, or storing the required data value for a write request). Further, any output generated by the other memory units that have been accessed, but which in hindsight need not have been, can be ignored.
For example, if a cache lookup took place and resulted in a cache miss, but the results of the analysis of the access request indicated that the data value was in a non-cacheable region of memory, then the fact that the cache miss occurred can be ignored, rather than invoking the usual procedure of performing a linefill to the cache. Similarly, if the address specified by the access request is outside of the range of the addresses stored within the TCM, then the TCM will still typically generate an output based on that portion of the address which is within the range of addresses for data stored within the TCM. However, once the analysis of the access request indicates that the data value is not within the TCM, that output from the TCM can be ignored.
Whilst from a performance point of view the above approach of speculatively accessing multiple memory units, and then qualifying their outputs based on the results of the analysis of the access request, enables the required performance for accesses to be achieved, such an approach consumes significant power, since more memory units are accessed that actually is required to perform the access request issued by the processor core. For example, in a system employing a cache and a TCM, if the access request actually specifies a data value contained within the TCM, then the cache will unnecessarily have been driven to perform an access, whilst similarly if the access request relates to a cacheable data value, the TCM will unnecessarily have been driven to perform the access.
Accordingly, it would be desirable to provide a more power efficient technique for performing memory accesses, which does not unduly impact performance.
SUMMARY OF THE INVENTION
Viewed from a first aspect, the present invention provides a data processing apparatus, comprising: a plurality of memory units for storing data values; a processor core for issuing an access request specifying an access to be made to the memory units in relation to a data value; a memory controller for performing the access specified by the access request; attribute generation logic for determining from the access request one or more predetermined attributes verify which of the memory units should be used when performing the access; prediction logic for predicting the one or more predetermined attributes; clock generation logic responsive to the predicted predetermined attributes from the prediction logic to select which one of the memory units is to be clocked during performance of the access, and to issue a clock signal to that memory unit; checking logic for determining whether the predetermi
Bull David Michael
Campbell Gary
Middleton Peter Guy
ARM Limited
Elmore Stephen
Nixon & Vanderhye P.C.
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