Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2004-08-13
2008-08-26
Portka, Gary J (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C709S216000, C711S146000
Reexamination Certificate
active
07418556
ABSTRACT:
A method for communicating between nodes of a plurality of nodes is disclosed. Each node includes a plurality of processors and an interconnect chipset. The method issues a request for data from a processor in a first node and passes the request for data to other nodes through an expansion port (or scalability port). The method also starts an access of a memory in response to the request for data and snoops a processor cache of each processor in each node. The method accordingly identifies the location of the data in either the processor cache or memory in the node having the processor issuing the request or in a processor cache or memory of another node. A method for requesting data between two directly coupled nodes in a router system is also disclosed. A method for requesting data between three or more nodes in an interconnect system is also disclosed. A method for resolving crossing cases in an interconnect system is also disclosed. An interconnect system for coupling nodes directly or through a protocol engine is also disclosed.
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Weber Wolf-Dietrich
Wilson James C
Fenwick & West LLP
Fujitsu Limited
Portka Gary J
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