Electrical computers and digital data processing systems: input/ – Interrupt processing – Handling vector
Reexamination Certificate
1999-11-29
2002-07-23
Follansbee, John A. (Department: 2154)
Electrical computers and digital data processing systems: input/
Interrupt processing
Handling vector
C712S244000
Reexamination Certificate
active
06425039
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data processor for executing an exception handling program to cope with the occurrence of exceptions such as reset event, exception events and interrupt events. More specifically, the invention relates to technology for shortening the time required for the transition from a moment of occurrence of an exception event to the operation of an exception handler for coping with the exception event. The invention relates to technology that can be effectively adapted to, for example, a single-chip microcomputer or a microprocessor contained in a memory management unit (MMU).
In processing the data using a central processing unit that is included in the data processor, there may often occur general exception events such as decoding of undefined instruction in an instruction set of the data processor, invalid arithmetic operation, protection violation in a virtual storage, TLB miss exception events, etc., as well as end signaling for informing the central processing unit of the end of data input/output operation in the peripheral circuits of the data processor and interrupt requests (referred to as general interrupt events) such as request of reception from a communication module in the data processor.
When exception events such as the above-mentioned general exception events and general interrupt events occur, the central processing unit suspends the execution of instructions of a data processing program, shifts the control to an exception handler to cope with exceptions that have occurred, executes the data processing specified by the exception handler, and works to cope with the exception events. After the exception handler is executed, the central processing unit retries the suspended instruction or returns to an instruction address next to the suspended instruction, and resumes the suspended data processing program. Therefore, if general exception events and general interrupt events occur, the central processing unit executes the operation to save values of a program counter therein and internal conditions of the status register into the stack regions of an external memory. When the processing of the central processing unit returns from the exception handler to the suspended data processing program, the central processing unit transfers the values saved in the program counter and the internal conditions of the status register from the stack regions of the external memory to the program counter and to the status register, respectively, and continues the suspended data processing program.
A predetermined data processing program has been branched to a predetermined exception handler by a method of fixing a variety of destination addresses (head memory addresses of a variety of exception handlers) using a hardware (logic circuit) or by a vector system which designates destination addresses from the central processing unit. According to the vector system, for example, a vector table storing head addresses of a variety of exception handlers for responding to an interrupt request is arranged on an external memory, a pointer (interrupt vector register) of the vector table is designated from the central processing unit, the head address of a corresponding exception handler is read out from the designated vector table, and a desired exception handler is read out from a position of the head address that is read out and is executed.
As a literature describing exception events such as interrupt requests, there can be cited “MICROCOMPUTER HANDBOOK”, Ohm Co., Dec. 25, 1987, pp. 177-178.
SUMMARY OF THE INVENTION
The above-mentioned vector system, however, requires the operation for reading the external memory to obtain a head address of a corresponding exception handler from the vector table from the occurrence of an exception event up to dealing with it. Therefore, the time required for the transition from the occurrence of the exception event to the branching to a corresponding handler increases by the amount of operation for reading the external memory. Moreover, when the data in the program counter, in the status register and in the general-purpose register are to be saved to the stack regions of the external memory prior to branching to a corresponding exception handler, response to the exception event is delayed even by the operation for writing data into the external memory.
In particular, a quick response to an exception event, related to TLB miss exception event that occurs in synchronism with the operation of the central processing unit, means that the time can be shortened from the moment of occurrence of TLB miss exception event to the retry of the suspended instruction. The present inventors have discovered that this is quite important for enhancing data processing performance of the central processing unit. This is because, though it is classified as an exception event, the TLB miss exception event is an event that usually occurs during the execution of a data processing program free from mistake and is substantially different from exception events that occur due to a mistake involved in the data processing program prepared by a user. Therefore, to quickly cope with TLB miss exception events is to improve data processing performance of the central processing unit.
A method can be further contrived to completely fix a variety of destination addresses by hardware. However, this method is little versatile for mapping the exception handlers related to the user description or for the program sizes, and is little convenient to use. It is further considered that the amount of hardware increases for forming destination addresses.
The object of the present invention is to provide a data processor which is capable of shortening a transition time of from the moment of occurrence of an exception event up to shifting or branching the processing into an exception handler for coping with it.
Another object of the present invention is to provide a data processor which is capable of providing the constitution of exception handler with freedom to respond to exception events.
A further object of the present invention is to provide a data processor which is capable of shortening the transition time for a processing such as of a TLB miss exception event which can make it possible to execute the data processing at high speeds, and is also capable of offering high degree of versatility for the mapping of exception handlers on the memory and for the memory sizes of the exception handlers concerning those exception events and interrupt events which may not much contribute to executing the data processing at high speeds so much as the TLB miss exception events.
A still further object of the present invention is to provide a low-cost and high-speed data processor capable of satisfying both contracting the physical circuit scale from the standpoint of handling exception events and executing the data processing at high speeds.
The above and other objects as well as novel features of the present invention will become obvious from the description of the specification and the accompanying drawings.
Among the inventions disclosed in this application, representative examples will now be briefly described below.
Referring to
FIG. 1
, a single-chip data processor comprises:
a storage circuit (EXPEVT, INTEVT) into which, in response to an exception event, an exception code assigned in advance to it (such as reset event, general exception events, general interrupt requests) is stored; and
a central processing unit (CPU) including a program counter (PC), and a control means (CTRL) which, in response to an exception event, writes a predetermined instruction address into said program counter so that a first exception handler assigned to said instruction address may be executed.
In accordance with a processing specified in the first exception handler, the control means calculates a second instruction address for branching into a second exception handler from the first exception handler by utilizing the exception code written into the storage circuit as an addre
Kawasaki Ikuya
Matsui Shigezumi
Narita Susumu
Yoshioka Shin-ichi
Follansbee John A.
Hitachi , Ltd.
Loudermilk & Associates
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