Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2011-05-24
2011-05-24
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Read/write circuit
Signals
C365S230030, C365S205000, C365S189050
Reexamination Certificate
active
07948816
ABSTRACT:
A memory is disclosed that comprises: an input for receiving an input signal and an output for outputting data; a plurality of data storage cells for storing individual units of data; said plurality of data storage cells being arranged in an array; a plurality of said arrays; each of said arrays comprising detecting circuitry for detecting and outputting stored data in response to a control signal received at said detecting circuitry; delay circuitry for providing a delay to said control signal sent to said detecting circuitry of at least some of said plurality of arrays, said delay provided to said control signal being longer for at least one array located closer to an input and output of said memory than it is to at least one array located further from an input and output of said memory.
REFERENCES:
patent: 5329492 (1994-07-01), Mochizuki
Min et al., “A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM”,4thIEEE International Symposium on Electronic Design, Test&Applications, 2008, pp. 107-110.
Amrutur et al., “A Replica Technique for Wordline and Sense Control in Low-Power SRAM's”,IEEE Journal of Solid-State Circuits, vol. 33, No. 8, Aug. 1998, pp. 1208-1219.
ARM Limited
Hoang Huan
Nixon & Vanderhye P.C.
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