Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller
Reexamination Certificate
1999-12-29
2003-04-08
Tung, Kee M. (Department: 2776)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Graphic display memory controller
C345S559000, C345S568000, C711S206000
Reexamination Certificate
active
06545684
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to storing data in a memory and to accessing that data.
Data is accessed from a memory, such as a graphics memory, on a row-by-row basis. Heretofore, this meant that the entire pitch of the memory had to be traversed each time the memory was accessed, regardless of how the data is stored in the memory. For example, referring to
FIG. 1
, to access data
1
, it was necessary to traverse the entire pitch
2
of memory
4
, row-by-row (arrows
5
), starting with top row
6
and working downward. A large portion of unused memory
7
is thus unnecessarily traversed.
SUMMARY OF THE INVENTION
In general, in one aspect, the invention relates to accessing data stored in a memory. This aspect of the invention features obtaining an indication that the memory is tiled, where a tile comprises a segment of the memory having a dimension that is less than a pitch of the memory, and accessing data stored in a target tile of the memory before accessing other segments of the memory.
Among the advantages of this aspect of the invention may be one or more of the following. Accessing data in a tiled memory reduces the need to traverse unused portions of memory, thus reducing the amount of time it takes to read data from the memory. Also, use of a tiled memory can reduce the amount of unused (wasted) memory, particularly if the tiles are based on the memory's page size.
Other features and advantages of the invention will become apparent from the following description and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1
is a view of a memory which stores data according to the prior art.
FIG. 2
is a view of a computer system on which one embodiment of the invention may be implemented.
FIG. 3
is a view of a tiled memory.
FIG. 4
is a flowchart showing a process for determining configuration data for a tiled memory.
FIG. 5
is a flowchart showing a process for reading data from a tiled memory.
FIG. 6
is a flowchart showing a process for allocating memory to be tiled.
FIG. 7
is a block diagram showing how memory is allocated according to the process of FIG.
6
.
REFERENCES:
patent: 6072507 (2000-06-01), Balatsos et al.
patent: 6247084 (2001-06-01), Apostol et al.
patent: 6362826 (2002-03-01), Doyle et al.
“Memory Management Support for Tiled Array Organization,” Gary Newman,Computer Architecture News, vol. 20, No. 4, Sep. 1992, pp 22-30.
Dragony Joseph M.
Sethi Prashant
Fish & Richardson P.C.
Tung Kee M.
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