Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-02-28
2006-02-28
Ray, Gopal C. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C370S402000, C711S202000
Reexamination Certificate
active
07007126
ABSTRACT:
An I/O subsystem having a processor, a bridge unit, and an I/O messaging unit that couple a primary, secondary and tertiary bus in a computer system. The bridge unit is configurable to claim requests that access a messaging unit (MU) address range from the secondary bus, the MU itself being coupled to the primary bus. The MU interrupts the processor when an I/O request is posted, in response to which the processor reads from the MU pointers to an I/O messages and may then execute the I/O message. To promote the portability of software written for agents on either the primary or the secondary bus that wish to access the MU, the primary and secondary address translation units of the I/O subsystem are programmed to claim the same address translation window, where the MU address range is a portion of the primary ATU address translation window, and the secondary ATU is configured to not claim requests within the MU address range. In a particular embodiment, the I/O subsystem may be implemented as a single integrated circuit chip (I/O processor) which is configured to support the intelligent I/O (I2O®) protocol in connection with Peripheral Components Interconnect (PCI) primary and secondary system busses. By configuring the bridge to claim the MU address range on the secondary bus, the I/O subsystem may permit agents on the secondary bus to perform the I2O protocol without interrupting the host processor which normally resides on the primary PCI bus.
REFERENCES:
patent: 5555383 (1996-09-01), Elazar et al.
patent: 5619728 (1997-04-01), Jones et al.
patent: 5734847 (1998-03-01), Garbus et al.
patent: 5734850 (1998-03-01), Kenny et al.
patent: 5774683 (1998-06-01), Gulick
patent: 5832245 (1998-11-01), Gulick
patent: 5838935 (1998-11-01), Davis et al.
patent: 5848249 (1998-12-01), Garbus et al.
patent: 5857080 (1999-01-01), Jander et al.
patent: 6047349 (2000-04-01), Klein
patent: 6128684 (2000-10-01), Okayama
patent: 6173383 (2001-01-01), Casamatta
patent: 6374321 (2002-04-01), Pawlowski et al.
patent: 6587868 (2003-07-01), Porterfield
patent: 6735659 (2004-05-01), Nakanishi et al.
patent: 6745369 (2004-06-01), May et al.
“Using SCAN Bridge as an IEEE 1149.31 protocol addressable, multidrop, backplane test bus” by J. Andrews (abstract only) Publication Date: Oct. 2-6, 1994.
“Design and implementation of a CAN/CAN bridge” by Ekiz et al. (abstract only) Publication Date: Jun. 12-14, 1996.
“The GIGAswitch control processor” by Walsh, R.J; Ozveren, C.M. (abstract only).
Davis Barry R.
Futral William
Gillespie Byron R.
LandOfFree
Accessing a primary bus messaging unit from a secondary bus... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Accessing a primary bus messaging unit from a secondary bus..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Accessing a primary bus messaging unit from a secondary bus... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3641065