Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Utility Patent
1997-10-28
2001-01-02
Yoo, Do Hyun (Department: 2759)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S148000, C711S149000, C711S150000, C711S168000
Utility Patent
active
06170046
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to memories, systems using memories, and methods for accessing memories.
To increase throughput of memory access operations, some data processing systems employ multi-ported memories. Multiple access operations are allowed to proceed in parallel through different ports to increase the throughput. However, the cost of memories increases with the number of ports. Therefore, it is desirable to use memories having fewer ports while still obtaining high throughput. Further, in memory systems with multi-ported memories, separate address and data buses are used for each port. It is desirable to reduce the number of address and data buses in the memory system.
It is also desirable to increase the address and data bus utilization in memories that use different timing for read and write operations. Such memories include fast synchronous SRAMs (static random access memories). Different timing for read and write operations causes address or data bus utilization penalty when the memory is switched from a write operation to a read operation or from a read to a write. It is desirable to reduce or eliminate such penalty.
It is also desirable to provide memory systems that enable one to obtain a non-blocking ATM (asynchronous transfer mode) switch, or some other switch, by combining two or more switch fabrics to increase the number of ports but without increasing the cost per port.
SUMMARY
Some embodiments of the present invention provide memory systems that allow multiple access operations to proceed in parallel. Some embodiments use memories with different timing for read and write operations. In particular, in some embodiments, each memory in the memory system allows pipelined read access such that when data are being read out of the memory in one read operation, a read address is provided to the memory for another read operation. However, in a write operation, the address and data are provided to the memory at the same time. (Some fast synchronous SRAMs have such timing.) Therefore, when the memory is switched from a write to a read or from a read to a write, there is utilization penalty with respect to memory address or data ports. However, in some embodiments of the invention, no penalty occurs with respect to the data buses of the memory system. In some embodiments, no penalty occurs also with respect to the address buses. Further, the number of ports in each individual memory is reduced. In some embodiments, each memory is single-ported. The number of data buses is also reduced by making the data buses shared between different ports. In some embodiments, the number of address buses is also reduced by making them shared.
These advantages are achieved in some embodiments by connecting an address bus to different address ports corresponding to data ports connected to different data buses, and/or connecting a data bus to different data ports corresponding to address ports connected to different address buses. In some embodiments, each combination of an address bus and a data bus can be used to access a separate memory.
For example,
FIG. 1
shows four single-ported memories
110
_UL,
110
_UR,
110
_DL,
110
_DR (FIG.
1
). Address bus mAddr_U is connected to the address ports of memories
110
_UR and
110
_UL, and address bus mAddr_D is connected to the address ports of memories
110
_DR and
110
_DL. Data bus Data_L is connected to the data ports of memories
110
_UL and
110
_DL, and data bus Data_R is connected to the data ports of memories
110
_UR and
110
_DR.
Each combination of an address bus and a data bus allows access to one of the four memories
110
.
The memory system is a shared memory in any flow switch, for example, an ATM (Asynchronous Transfer Mode) switch composed of two switch fabrics. The two address buses and the two data buses allow a write and a read to proceed in parallel. In each clock cycle, an ATM cell is written by one of the switch fabrics into one of the memories
110
for storage before transmission, and another cell is read by the other fabric from another one of the memories for transmission. A cell can be written into any memory available for a write operation. Each switch fabric has the same number of ports. Hence, when the switch fabrics are combined, the number of ports is doubled. However, the cost per port is about the same as in a single switch fabric.
Each memory is a synchronous SRAM allowing pipelined reads. A read operation latency is two clock cycles, with one cycle for the address and one cycle for the data. A write operation latency is one cycle. However, both of the address buses and both of the data buses can be used in every cycle. The bus utilization penalty is avoided as follows.
In each clock cycle, one address bus and one data bus can be taken by read operations. (More particularly, in each clock cycle, one address bus can carry an address for a read operation started in this cycle, and one data bus can carry data for a read operation started in the previous cycle). Therefore, in each clock cycle, one address bus and one data bus remain available for a write operation. No utilization penalty occurs.
The invention is not limited to two address buses or two data buses, or to four memories, or to any particular number of clock cycles needed for a read or a write.
Some embodiments provide mirror-image memories that duplicate each other. Some such embodiments allow multiple reads to occur in parallel. Thus, some embodiments are used in an ATM switch in which two reads and two writes can proceed in parallel. If two cells to be read out simultaneously are stored in the same memory, they are also stored in the mirror-image of that memory, and hence each cell can be read out from a different memory. Therefore, the two cells can be read out simultaneously even if each memory is single-ported.
When a cell is written into any memory, it is also written into the mirror image of that memory.
Some embodiments provide more than one mirror images for each memory. For example, in some embodiments, a switch can read four cells simultaneously, and each memory has three mirror image memories such that all the four memories store the same data. Each memory is single-ported. If more than one cells to be read out simultaneously are stored in the same memory, these cells are read out from different memories that are mirror images of each other. Alternatively, in some embodiments each memory has only one mirror image, but each memory is double-ported, and hence four cells stored in the same memory can be read out from the memory and its mirror image simultaneously.
In some mirror-image embodiments, no memory allows pipelined read or write operations, for example, each memory is an asynchronous SRAM. Other embodiments allow pipelined reads or writes or both.
The invention allows a non-blocking ATM switch performing multiple accesses to a shared memory in parallel to be easily constructed from switch fabrics each of which performs at most one shared-memory access at any given time.
The invention is not limited to ATM switches or to networks.
Other features and advantages of the invention are described below. The invention is defined by the appended claims.
REFERENCES:
patent: 4744078 (1988-05-01), Kowalczyk
patent: 4750154 (1988-06-01), Lefsky et al.
patent: 4754451 (1988-06-01), Eng et al.
patent: 4760570 (1988-07-01), Acampora et al.
patent: 4888741 (1989-12-01), Malinowski
patent: 4891794 (1990-01-01), Hush et al.
patent: 4891795 (1990-01-01), Pinkham et al.
patent: 5142638 (1992-08-01), Schiffleger
patent: 5204841 (1993-04-01), Chappell et al.
patent: 5278967 (1994-01-01), Curran
patent: 5337287 (1994-08-01), Nishikawa
patent: 5432907 (1995-07-01), Picazo, Jr. et al.
patent: 5440523 (1995-08-01), Joffe
patent: 5490263 (1996-02-01), Hashemi
patent: 5634004 (1997-05-01), Gopinath et al.
patent: 5651129 (1997-07-01), Yokote et al.
patent: 5856940 (1999-01-01), Rao
patent: 5875470 (1999-02-01), Dreibelbis et al.
patent: 5907864 (1999-05-01), Potts et al.
patent: 5920898 (1999-07-01), Bolyn et al.
paten
Birger Ari
Joffe Alexander
MMC Networks, Inc.
Portka Gary J.
Shenker Michael
Skjerven Morrill & MacPherson LLP
Yoo Do Hyun
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