Access time speed-up circuit for a semiconductor memory device

Static information storage and retrieval – Addressing – Byte or page addressing

Patent

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Details

36518905, G11C 800

Patent

active

053982134

ABSTRACT:
A semiconductor memory device includes two latch circuits, each for holding data corresponding to a single normal address. When sequentially used, one after the other, one latch circuit can be storing new data while the other latch circuit outputs its data to the page decoder for subsequent output. Thus, data access delay times for page mode operation are further reduced because the delay which typically results from addressing a normal address is eliminated.

REFERENCES:
patent: 5305284 (1994-04-01), Iwase

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