Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1998-03-12
2001-07-24
Decady, Albert (Department: 2133)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C714S721000
Reexamination Certificate
active
06266749
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to electronic circuits, and more specifically to semiconductor integrated circuits.
BACKGROUND OF THE INVENTION
The measurement of access time in memory circuits is one of the most difficult items in integrated circuit testing. Access time is generally defined as the delay between the inputting of information to a memory circuit and the presence of valid data at the output of the memory circuit. One common parameter is the address access time, that is, the amount of delay between providing a memory cell address and the availability of the stored data at the output of the circuit. The address access times for static random access memory circuits (SRAMs) and dynamic random access memory circuits (DRAMs) are on the order of tens of nanoseconds. The brevity of the access time parameter is one factor in making the measurement difficult.
Techniques used in the past have typically relied on two or more clock signals to measure access time. This is particularly so for synchronous circuits, that is, memory devices in which the transfer of information into, within, and out of the circuit is coordinated with a clock signal. In one example of an access time measurement using multiple clocks, one clock signal is used to regulate the latching of address information and the propagation of signals within the memory circuit, while a second clock is used to regulate the outputting of data.
The multiple-clock approaches suffer from several problems. For example, die space is consumed by the pads and lines associated with additional clocks. This additional space on an integrated circuit die that is devoted only to testing the integrated circuit is often referred to as “test overhead.” In addition, in a system that relies on two or more clocks, the propagation delay differences between the clock signals affect the accuracy of the access-time measurement. A need exists in the industry for a solution to these problems.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the invention, there is disclosed a circuit for measuring the access time of a memory circuit. The circuit includes a storage element having an input terminal, an output terminal, and a clock terminal. The input terminal of the storage element is coupled to an output of the memory circuit. A clock signal source is coupled to the clock terminal of the storage element and to a clock terminal of the memory circuit. The circuit also includes test circuitry coupled to address and control terminals of the memory circuit and to the output terminal of the storage element. The test circuitry is operable to store a test data pattern, or alternatively to generate a test pattern, and compare the pattern to data output from the storage element. In one embodiment, the storage element is a data latch comprising a clock-enabled inverter serially coupled with a flip-flop. The flip-flop in one embodiment is a cross-coupled inverter storage cell or “keeper”. For a clock signal having a pulse length or duty cycle that is longer than the access time of the memory circuit, the output of the storage element matches the data pattern stored by the test circuitry. As the clock frequency is increased, or the duty cycle decreased, so that the pulse length approximates the access time, the data output from the storage element no longer matches the data expected by the test circuitry, thus allowing a determination of the access time.
An advantage of the inventive concepts is that an access time measurement is possible using a single clock signal. Thus, test overhead on the integrated circuit is kept to a minimum and problems with differing delays between clock signals are avoided. In addition, no extra package pins or terminals are required by the measurement approach.
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Hall James N.
Hashimoto Masashi
Brady III Wade James
De'cady Albert
Rountree Robert N.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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