Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-10-30
2001-10-16
Etienne, Ario (Department: 2155)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S036000, C710S120000, C710S240000
Reexamination Certificate
active
06304931
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a bus control system and to a bus control method that do not permit an access request, to other arbitrary access request responding units, during a period from an access request from an access requesting unit, such as a microprocessor or a CPU (Central Processing Unit) connected to a common bus including a data bus or an address bus, to a specific access request responding unit, until a completion of the access request.
The common bus applied to such a bus control system is generally referred to as a “non-split bus”. When a read operation of data and a write operation of data are executed between an access requesting unit, such as a CPU (Central Processing Unit) connected to this non-split bus, and access request responding units such as a memory and an I/O, the present invention pertains to one technique for improving, as much as possible, the utilization efficiency of the non-split bus.
2. Description of the Related Art
A read operation of a bus control system according to the prior art will be explained hereby with reference to
FIG. 1
, that will be described later in “Brief Description of the Drawings”, in order to demonstrate the problems encountered when a read operation of data and a write operation of data are executed in conventional bus control systems using a non-split bus.
However, in this case, it is assumed that a conventional bus control system of a type in which a CPU having the function of generating a series of access requests (i.e., an access requesting unit) and a memory and an I/O for inputting and outputting the data in response to the access request from the CPU (i.e., access request responding units), are connected to a common bus of a non-split type including the data bus or the address bus described above.
In
FIG. 1
, a timing chart useful for explaining the read operation of the conventional bus control system is illustrated. This timing chart shows only those signals which are necessary for transferring the data between the CPU, and the memory and the I/O.
When the read operation of data is executed (i.e., at the time of the read operation of data), the CPU on the data read requesting side outputs an address (A
1
) on the address bus and an address strobe signal /AS (where “/AS” represents a signal of a negative logic). Either one of the memory and the I/O on the responding side to the data read request from the CPU receives the address (A
1
) described above, and outputs the data (D
1
) on the data bus and the data strobe signal /DS (where “/DS” represents a signal of a negative logic) at the time when the output of the data (D
1
) becomes feasible. Incidentally, the address strobe signal /AS and the data strobe signal /DS each having a negative logic become an active state (become effective) at an “L (low)” level, that is, at a low voltage level, and become an inactive state at a “H (high)” level, that is, at a high voltage level. Further, the CPU reads the data (D
1
) from the data bus at the time when the data strobe signal /DS becomes effective.
Thereafter, the CPU on the data read requesting side outputs the next address (A
2
) on the address bus and outputs the address strobe signal /AS. Either one of the memory and the I/O on the responding side to the data read request from the CPU receives the address (A
2
), outputs the data (D
2
) on the data bus at the time when the output of the next data (D
2
) becomes feasible, and outputs the data strobe signal /DS. Further, the CPU reads the data (D
2
) from the data bus at the time when the data strobe signal /DS becomes feasible. A series of these sequences concerning the read operation are executed until the data read request from the CPU is finished.
When the write operation of data is executed (i.e., at the time of the write operation of data, which is not shown in the drawing), on the other hand, the CPU on the data write requesting side outputs the address on the address bus and also outputs the address strobe signal /AS. Either one of the memory and the I/O on the responding side to the data write request from the CPU receives the address and outputs the data strobe signal /DS at the time when the input of the data described above becomes feasible. Further, the CPU outputs the data in response to the data strobe signal /DS, and either one of the memory and the I/O receives and inputs the data.
Thereafter, the CPU on the data write requesting side outputs the next address to the address bus and outputs the address strobe signal /AS. Either one of the memory and the I/O on the responding side to the data write request from the CPU receives the address and outputs the data strobe signal /DS at the time when the input of the next data becomes feasible. Further, the CPU outputs the next data in response to the data strobe signal /DS. A series of these processes concerning the write operation are executed until the data write request from the CPU is finished.
In both of the read and write operations described above, the time which has elapsed from the output of the address strobe signal /AS from the CPU till the return of the data strobe signal to the CPU, corresponds to the processing time inside the memory and the I/O on the responding side to the data read request and the data write request.
As described above, when the read and write operations of data are executed in the conventional bus control system, the next data read request and the next data write request cannot be generated until the CPU on the access requesting side outputs the address strobe signal and then receives the data strobe signal. For this reason, the utilization efficiency of the bus becomes low. In other words, even though a control circuit inside the memory or the I/O on the responding side to the access request enters into the state in which it can execute an addressing process for responding to the next access request in a period from the output of the address strobe signal until the output of the data strobe signal, wasted time or latency corresponding to the above period occurs because the address for the next access request does not arrive at the control circuit.
SUMMARY OF THE INVENTION
The present invention has been conceived of in view of the problems described above, and is directed to improving the utilization efficiency of the bus by reducing as much as possible the wasted time occurring when the address for the next access request from the CPU, etc., on the access requesting side does not arrive at the memory and the I/O or the like.
To solve the problems described above, a bus control system according to the present invention is constituted so as to include one access requesting unit connected to a common bus including a data bus or an address bus; and a plurality of access request responding units for responding to an access request from this access requesting unit, and constituted so as not to permit an access request to other arbitrary access request responding units, in a period from an access request to a specific access request requesting unit from the access requesting unit, until a completion of the access request. In such a configuration, when a read operation is executed, the specific access request responding unit includes a next-address enable signal generating unit for sending a next-address enable signal, which represents that the next address can be received, to the access requesting unit before data is transferred to the data bus, in accordance with an address representing the access request from the access requesting unit.
Preferably, the access requesting unit in the bus control system according to the present invention includes a next-address enable signal receiving unit for receiving the next-address enable signal from the specific access request responding unit and for sending the next address to the specific access request responding unit.
Further, the bus control system according to the present invention is constituted so as to include one access requesting unit connected to a common bus including a data
Arent Fox Kintner & Plotkin & Kahn, PLLC
Etienne Ario
Fujitsu Limited
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