Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2000-11-09
2004-05-25
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S154000, C709S241000, C709S241000, C710S048000, C710S120000, C710S260000, C710S261000, C710S264000, C710S267000
Reexamination Certificate
active
06742089
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an access controller and an access method and, more particularly, to an access controller and an access method for controlling access from a CPU (Central Processing Unit) to a memory.
BACKGROUND ART
FIG. 5
is a block diagram partly illustrating a structure of a prior art information processor. This Figure shows a structure associated with access from a CPU
160
or first and second processing circuits
500
and
510
to a DRAM (Dynamic Random Access Memory)
120
.
The information processor as shown in
FIG. 5
comprises the CPU
160
, an access port
140
, the DRAM
120
, a bus arbiter
130
, and the first and second processing circuits
500
and
510
. Assume that the access port
140
, the DRAM
120
, the bus arbiter
130
, and the first and second processing circuits
500
and
510
are manufactured on an LSI
110
.
The CPU
160
controls the whole operation of the information processor. The DRAM
120
is a memory on which information associated with the operation of the information processor is written, which retains the information, and from which the information is read. When access to the DRAM
120
is requested by the CPU
160
and the first and second processing circuits
500
and
510
, the bus arbiter
130
authorizes the access in order of descending priorities. The access port
140
comprises a register on which the information associated with the access request to the DRAM
120
output by the CPU
160
is written, and transmits the access request to the bus arbiter
130
. The first and second processing circuits
500
and
510
are arbitrary processing circuits, and therefore the number of these circuits is not restricted to two.
FIG. 6
is a block diagram illustrating a structure of the access port
140
. The access port
140
comprises a DRAM byte address specifying register
141
, a DRAM word data reading/writing register
142
, and an access mode specifying register
143
. The access mode specifying register
143
comprises a DRAM address variability specifying bit
144
and a DRAM address increase/decrease specifying bit
145
.
The DRAM byte address specifying register
141
is a register on which an address in the DRAM that the CPU
160
intends to access is written. The DRAM word data reading/writing register
142
retains the data of the address that has been written on the DRAM byte address specifying register
141
or data to be written at the address that has been written on the DRAM byte address specifying register
141
. The access mode specifying register
143
specifies how to access the DRAM
120
. The DRAM address variability specifying bit
144
specifies by 1 or 0 whether the address that has been written on the DRAM byte address specifying register
141
is to be consecutively varied or not. The DRAM address increase/decrease specifying bit
145
specifies by 1 or 0 whether the address that has been written on the DRAM byte address specifying register
141
is to be consecutively increased or decreased. address variability specifying bit
144
specifies by 1 or 0 whether the address which has been written on the DRAM byte address specifying register
141
is to be consecutively varied or not. The DRAM address increase/decrease specifying bit
145
specifies by 1 or 0 whether the address which has been written on the DRAM byte address specifying register
141
is to be consecutively increased or decreased.
Next, the access operation will be described with reference to
FIGS. 5 and 6
.
When the CPU
160
intends to read data at a predetermined address, for example an address of 0×0500, 0 is written on the DRAM address variability specifying bit
144
and the address of 0×0500 is written on the DRAM byte address specifying register
141
. When the CPU
160
accesses contiguous addresses, for example addresses of 0×0500 to 0×0508, 1 is written on the DRAM address variability specifying bit
144
, 1 is written on the DRAM address increase/decrease specifying bit
145
, and the address of 0×0500 is written on the DRAM byte address specifying register
141
. In addition, when the CPU
160
accesses contiguous addresses in descending order, for example the addresses from 0×0508 to 0×0500, 1 is written on the DRAM address variability specifying bit
144
, 0 is written on the DRAM address increase/decrease specifying bit
145
, and the address of 0×0508 is written on the DRAM byte address specifying register
141
.
The CPU
160
outputs the access request to the bus arbiter
130
via the access port
140
. When the access to the DRAM
120
is also requested by the first and second processing circuits
500
and
510
, the bus arbiter
130
compares the request of the CPU
160
with the requests of the first and second processing circuits
500
and
510
, and authorizes the access to the address for the request having the highest priority. For example, when the priority of the request by the CPU
160
is the highest, the bus arbiter
130
accesses the address requested by the CPU
160
. The data at the accessed address are read into the DRAM word data reading/writing register
142
. When the CPU
160
accesses the DRAM word data reading/writing register
142
, it can read the data at the address for which the access request is made. At this time, when 0 has been written on the DRAM address variability bit
144
, the reading is terminated. When 1 has been written on the DRAM address variability bit
144
, the address which has been written on the DRAM byte address specifying register
141
is incremented or decremented in accordance with the specification of the DRAM address increase/decrease specifying bit
145
. The data at the incremented or decremented address are read into the DRAM word data reading/writing register
142
via the bus arbiter
130
.
When the CPU
160
intends to write data at a predetermined address in the DRAM
120
, the CPU
160
writes the address on the DRAM byte address specifying register
141
and thereafter writes data to be written on the DRAM word data reading/writing register
142
. When the CPU
160
accesses the requested address via the bus arbiter
130
, the data which have been written on the DRAM word data reading/writing register
142
are written at the accessed address. When the CPU
160
intends to write data at contiguous addresses, the address in the DRAM byte address specifying register
141
is incremented or decremented using the above-mentioned DRAM address variability bit
144
and DRAM address increase/decrease specifying bit
145
. Each time the address is incremented or decremented, the data which are to be written are written on the DRAM word data reading/writing register
142
. Accordingly, the data can be consecutively written at the predetermined addresses.
Japanese Published Patent Application No.Hei.2-253440 discloses a time division multitask execution device which executes tasks which are written on plural register files with switching the tasks, using firmware.
When an access request to the DRAM
120
is output for the plural tasks of CPU multitask processing or interrupt processing while the CPU
160
accesses the DRAM
120
via the access port
140
, the access, which has been executed until then, is interrupted. Then, information that is retained in the respective registers in the access port
140
is updated according to the tasks of the CPU multitask processing or interrupt processing.
However, in the above-mentioned system for accessing the DRAM
120
according to the prior art, even when the interrupted access is resumed, the address or data that has been updated in the middle may remain for some reason, whereby erroneous processing is executed.
For example, in order to execute a task of reading data at an address of 0×0500 in the DRAM, the CPU
160
writes 0 on the DRAM address variability specifying bit
144
and writes 0×0500 on the DRAM byte address specifying register
141
. Here, when the interrupt processing is commanded immediately before the CPU
160
reads data of the DR
Imamura Yasushi
Inoue Takao
Padmanabhan Mano
Song Jasmine
Wenderoth , Lind & Ponack, L.L.P.
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