Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2000-06-14
2004-02-17
McLean-Mayo, Kimberly (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C365S218000
Reexamination Certificate
active
06694402
ABSTRACT:
The invention relates to a method for controlling the access, in a computer, for memory having a number of erases that are limited on a block basis and containing user memory blocks, which are available for a user's access, by means of an address conversion.
It is known that memory with a limited erase frequency, because of the usually significant variations in the utilization of individual memory segments and in order to provide for a better utilization of their limited number of uses, is divided into individually erasable memory blocks, which are accessed in terms of addresses by means of an address conversion in such a manner that, when the memory is first used, a number of reserve blocks are exempted from addressing, which are gradually placed into operation by means of a substitute address assignment one after another only when one of the blocks that was used until then is completely expended and has become useless. This process therefore limits the available number of blocks to begin with and leaves a large number of more or less expended, i.e., incompletely used blocks after the reserve blocks have been used up. Also, determining whether a certain address is to be replaced with another address from the reserve area becomes increasingly more complex as the number of expended blocks increases.
It is furthermore known to adjust the write time and/or the erase time to the respective aging condition of the memory.
It is the object of the invention to reveal a method whereby no blocks are kept in reserve and an almost complete, uniform utilization of the erasability of the blocks is attained.
This object is met with the address conversion taking place via a pointer table, and with an erase utilization class being maintained, assigned to each address pointer, in the form of a table and increased each time a predefined erase-state criterion is reached, after which the other erase utilization class entries are searched in the pointer table for the lowest erase utilization class with a minimum distance from the current erase utilization class, and if such an erase utilization class is found the respective address pointer and the erase utilization class are swapped with those in the initial pointer position, and the respective user memory block contents that belong to these address pointers are swapped as well.
Advantageous designs are presented in the subclaims.
Since no memory blocks that are defective at the beginning due to manufacturing defects are occupied in the address table, this novel method results in virtually all useable memory blocks being utilized close to the limit of their maximum number of erases; read-outs are possible virtually without limit; before a new content is written an erase must take place. Long before a given memory block reaches the end of its useful life it is correlated with an address that has been used less frequently in terms of erases, and an even less frequently erased block is accordingly correlated with the previously more heavily used address. In this manner there is virtually never a failure due to overuse and the reliability of the system is greatly enhanced. There are usually between 0-2% blocks that fail initially, and the permissible number of erase cycles is, for instance, 1 million. The indirect addressing is, therefore, used on one hand to exclude those blocks from being used that fail initially, and additionally to ensure a nearly complete exhaustion of the useful life capacity of the functioning blocks.
To equalize the wear of the blocks caused by the erase operations, an access program is used, which performs the wear monitoring for the individual blocks, as well as the address conversions and the management and backup of the address tables, both during boot-up of the computer as well as during each erase operation.
The respective current entry of the erase utilization class for a previously erased user memory block is made on the basis of various erase-state criteria, which can be used separately or together.
A modulo count of all erase operations of a given user memory block serves as a first erase-state criterion, for which at least one modulo counter is kept in the respective user memory block and incremented with each erase operation and used for incrementing the erase utilization class entry with each modulo pass.
The given required write time and/or erase time serves as a further erase-state criterion. It is/they are either increased each time after a subsequent verification has shown that the write or erase operation was incomplete, or determined memory-internally according to another system-dependent aging pattern.
The higher the write and/or erase time, the higher the erase utilization class entry that is made. With a memory-internal write or erase time generation, the length of time is determined in a time pulse counter, the final reading of which is then used each time as an erase-state criterion.
Furthermore, noticeable signs of wear that have resulted in a data read-out error that can be restored by redundancy are taken into consideration in such a way that an increased degradation is attached to such blocks with each occurrence of a restorable error.
The address and wear data are kept in the memory or in the memory block itself, so that the latter are correlated with the wear history during their entire life and cannot be lost or decorrelated during an exchange of memory, e.g., from one computer to another.
To be able to locate the address and wear data an anchor block is provided, which is set up in the first useable physical memory block with the first available address and can be located based on an identity number stored therein. In this anchor block a pointer to the program code is provided, and a table containing the pointers to the other block pointers or also sector pointers, if the blocks are divided into sectors, as well as to their duplicates, which are created for safety.
The block and sector address pointers are kept in designated memory blocks. These block pointers and sector pointers are stored there in the sequence of their own logical addresses in the form of a pointer table. In a different sector of the same block the corresponding erase utilization class entries are made in parallel, with the same addresses. A duplicate of the entire block serves as backup and offers the possibility to reconstruct an incomplete content, which could occur if a power outage occurs exactly during a reallocation.
The grouping of a plurality, e.g., 16, sectors of e.g., 512 bytes into a block that will be erased in its entirety keeps the memory requirement for the pointer tables within narrow limits, so that approximately 99.8% of the functioning blocks are useable.
Memory usually consists of numerous memory chips, which, in turn, contain numerous blocks. The block pointer, therefore, comprises a chip address portion and a block address portion, which are stored in combination with one another. These addresses are advantageously stored as binary numbers that are factored by element by powers of two. For example, 256 block addresses are stored consecutively in one sector of the address pointer table, and four such sectors are chained together for a total of 1024 block addresses.
The user data are advantageously divided within the blocks into sectors and within same into data strings. These sectors preferably have a length of 512 bytes plus a number of spare bytes as check bytes for error checking and error correction, as well as the modulo counter for the erase operations. Each data string can have a varying length and usually contains between 100 and 200 bytes, each with four check bytes attached, so that two to four of the strings fit into one block.
If sectors have been erased, the check syndromes, e.g., Reed Solomon Codes, are invalid. The test circuit reports a corresponding condition for further evaluation. When other sectors of this block are newly written, sectors that have been erased but are not to be provided with a new content, must not be written to; rather they must be excluded from being written to,
Hyperstone AG
McLean-Mayo Kimberly
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