Accepting link ID upon supplied and sampled bits matching

Details Accepting link ID upon supplied and sampled bits matching Accepting link ID upon supplied and sampled bits matching

2005-12-02

2010-10-05

Guyton, Philip (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S727000

Reexamination Certificate

active

07809987

ABSTRACT:
An identification (ID) process comprises in each of a plurality of bit times, a debug test system asserting a control signal at a predefined state to a plurality of target systems, and each target system, having a bit pattern and the bit patterns being different among the target systems, outputting a bit from its bit pattern on the control signal. The process further comprises each target system comparing the resulting state of the control signal to that target system's output bit. If the target system's output bit differs from the resulting control signal state, the target system ceases participating in the ID process or, if the target system's output bit matches the resulting control signal state, the target system continues to participate in the ID process.

REFERENCES:
patent: 5787012 (1998-07-01), Levitt
patent: 5844803 (1998-12-01), Beffa
patent: 6321329 (2001-11-01), Jaggar et al.
patent: 6581190 (2003-06-01), Dixon et al.
patent: 6792365 (2004-09-01), Raitter

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